Si5338Q-A-GM Silicon Laboratories Inc, Si5338Q-A-GM Datasheet - Page 41

• Manufacturer Part Number: Si5338Q-A-GM
• Description: Clock Generators & Support Products I2C-prgrmmbl clock generatr .16-200 MHz
• Manufacturer: Silicon Laboratories Inc

Specifications of Si5338Q-A-GM

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

D
Revision 0.1 to 0.2
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Revision 0.2 to 0.3
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Revision 0.3 to 0.5
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Revision 0.5 to 0.55
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OCUMENT
Updated block diagram to show Rn output divider
and PLL bypass mode
Updated pin description to include FDBK±
Updated Table 3. DC Characteristics
Updated Table 12. Jitter Specifications
Added Supply Current vs. Output Frequency
Updated package outline specification
Clarified input clock configuration register settings
Updated DRV_INVERTn[1:0] settings
Added PLL bypass mode
Added LOS_FDBK description
Added additional detail to phase increment/
decrement and frequency increment/decrement
descriptions
Clarified output driver powerdown options
Clarified entry to self-calibration mode
Updated ordering guide
Changed minimum output clock frequency from
5 MHz to 1 MHz.
Updated slew rates.
Updated " Features" on page 1.
Updated Table 6, “Input and Output Clock
Characteristics,” on page 8.
Deleted Table 12, “Output Driver Slew Rate Control”.
Major editorial changes to all sections to improve
clarity
Completed electrical specification tables with final
characterization results
Revised the maximum input and output frequencies
from 700 MHz to 710 MHz
Improved jitter specifications to reflect updated
characterization results
Added new Si5338N/P/Q ordering codes
Added typical application diagrams
Added an application section to highlight the
flexibility of the Si5338 in various timing functions
Added a configuration section to clarify configuration
options
Editorial changes to section 3.5 “Configuring the
Si5338” to improve clarity on ordering custom
Si5338 and on configuring “blank” Si5338.
Added pin numbers to device package drawings.
Updated ordering information to include evaluation
boards.
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Rev. 1.0
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Revision 0.55 to 0.6
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Revision 0.6 to 0.65
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Revision 0.65 to 1.0
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Updated first page description and applications
Added 
Added GbE RM jitter specification with 1.875–
20 MHz integration band.
Changed output duty cycle to 45–55%.
All I
Changed ordering information to reflect 710 MHz
limit.
Info on POR and soft reset added.
Updated Figure 15 on page 26.
Added register section.
Update programming procedure in “3.5. Configuring
the Si5338” to improve robustness.
Updated Figure 9 to include the entire programming
procedure.
Added "3.2.1. Loss-of-Signal (LOS) Alarm
Detectors" on page 17 to show the location of the
LOS detector circuits.
Updated input circuit diagrams in "3.2. Input Stage"
on page 17.
Update block diagrams with new input circuit
diagrams.
Updated Figure 9, “I2C Programming Procedure,” on
page 21 for consistency with register description.
Expanded PCI jitter specifications in Table 12.
Moved “Si5338 Registers” section to AN411.
Added I
Revised CMOS output currents down for each
CMOS driver that is active in Table 3.
Clarified CMOS output loads in Table 3
Added peak reflow temperature and footnote in
Table 2.
Added sticky and mask register info in "3.6. Status
Indicators" on page 22.
Added more information to Table note about CMOS
outputs and jitter in Table 12.
Changed all reference of MultiSynth Mn to MSn
Added "11. Top Marking" on page 39.
Reworded 3.5.2 and 3.5.3 for clarity.
2
C address now in binary.
2
JC
C data rate specifications to Table 14.
to specification tables.
Si5338
41