MAX3878EHJ-T Maxim Integrated Products, MAX3878EHJ-T Datasheet - Page 11

• Manufacturer Part Number: MAX3878EHJ-T
• Description: Timers & Support Products 2.5Gbps, +3.3V Clock and Data Retiming I
• Manufacturer: Maxim Integrated Products
• Type: Clock and Data Retimingr

Specifications of MAX3878EHJ-T

• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Current: 163 mA
• Package / Case: TQFP-32 EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 1. Selecting Input Path
Figure 8. Open-Loop Transfer Function
Figure 9. Closed-Loop Transfer Function
LREF = 0
LREF = 1
H
H(j2πf) (dB)
O
-3
(j2πf) (dB)
2.5Gbps, +3.3V Clock and Data Retiming ICs
0
(Normal Operation)
C
f
(Holdover Mode)
Z
F
= 2.6kHz
1
= 1.0µF
1
______________________________________________________________________________________
SIS = 0
SLBI
SDI
10
C
F
10
= 1.0µF
100
C
f
Z
C
F
= 26kHz
F
= 0.1µF
= 0.1µF
100
1000
(System Loopback Mode)
(Holdover Mode)
1000
SIS = 1
SLBI
SLBI
with Vertical Threshold Adjust
f (kHz)
f (kHz)
The MAX3877/MAX3878 are designed for both regenera-
tor and receiver applications. The fully integrated PLL is a
classic second-order feedback system, with a loop band-
width (f
can be adjusted to set the loop damping. Figures 8 and 9
show the open-loop and closed-loop transfer functions.
The PLL zero frequency, f
capacitor C
For an overdamped system (f
ing (M
by:
For example, using C
of 0.16dB. Reducing C
instability. The recommended value of C
guarantee a maximum jitter peaking of less than 0.1dB.
C
or better.
Inputs for the MAX3877/MAX3878 are current-mode logic
(CML) compatible. The inputs all provide internal 50Ω ter-
mination to reduce the required number of external com-
ponents. When interfacing to differential PECL levels, it is
important to attenuate the signal while maintaining a 50Ω
termination (see Figure 10). AC-coupling is also neces-
sary to maintain the input common-mode level.
The MAX3877 uses current-mode logic (CML) for its high-
speed digital outputs. CML outputs are 50Ω back-termi-
nated, reducing the external component count. Refer to
Figure 11 for the output structure. CML outputs may be
terminated by 50Ω to V
ance.
The MAX3878 uses positive emitter-coupled logic (PECL)
for its high-speed outputs. PECL outputs are designed to
be terminated by 50Ω to (V
Note HFAN 0.1.0, Interfacing Between CML, PECL, and
LVDS, for more information.
F
must be a low-TC, high-quality capacitor of type XR7
P
) of a second-order system can be approximated
L
) fixed at 1.4MHz. The external capacitor, C
F
, and can be approximated according to:
M
Output Termination (MAX3877)
Output Termination (MAX3878)
P
f
Z
=
=
F
20
CC
F
= 0.1µF results in a jitter peaking
2 60
log
below 0.01µF may result in PLL
π(
, or by 100Ω differential imped-
CC
Setting the Loop Filter
Design Procedure
1



Z
Z
1
, is a function of external
)
C
+
- 2V). Refer to Applications
/ f
F
f
f
L
Z
L
Input Termination
< 0.25), the jitter peak-



F
= 1.0µF is to
11
F
,