DS1374C-18 Maxim Integrated Products, DS1374C-18 Datasheet - Page 14
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DS1374C-18
Manufacturer Part Number
DS1374C-18
Description
Real Time Clock I2C-Compatible 32-Bi t Binary Counter Wat
Manufacturer
Maxim Integrated Products
Datasheet
1.DS1374U-33.pdf
(18 pages)
Specifications of DS1374C-18
Function
Clock, Calendar, Elapsed Time Counter, Watchdog Timekeeper
Supply Voltage (max)
1.89 V
Supply Voltage (min)
1.71 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Rtc Bus Interface
Serial
Package / Case
SOIC-16
Time Format
Binary
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DS1374C-18+
Manufacturer:
VISHAY
Quantity:
4 186
The DS1374 supports the I
that sends data onto the bus is defined as a transmitter
and a device receiving data is a receiver. The device
that controls the message is called a master. The
devices that are controlled by the master are slaves. A
master device that generates the serial clock (SCL),
controls the bus access, and generates the START and
STOP conditions must control the bus. The DS1374
operates as a slave on the I
bus are made through the open-drain I/O lines SDA
I
Trickle Charger and Reset Input/Output
Figure 7. Programmable Trickle Charger
Figure 8. I
14
2
C, 32-Bit Binary Counter Watchdog RTC with
____________________________________________________________________
SDA
SCL
CONDITION
2
C Data Transfer Overview
START
MSB
V
TCS3
BIT 7
CC
1
I 2 C Serial Data Bus
NOTE: ONLY 1010b
ENABLES CHARGER
TCS2
BIT 6
1 OF 16 SELECT
2
2
2
SLAVE ADDRESS
C bus protocol. A device
C bus. Connections to the
TCS1
BIT 5
TCS0
BIT 4
6
BIT 3
DS1
7
SELECT
1 OF 2
DIRECTION
BIT 2
DS0
R/W
BIT
8
SIGNAL FROM RECEIVER
ACKNOWLEDGEMENT
ROUT1
BIT 1
SELECT
1 OF 3
ACK
ROUT0
9
BIT 0
and SCL. A standard mode (100kHz max clock rate)
and a fast mode (400kHz max clock rate) are defined
within the bus specifications. The DS1374 works in both
modes.
The following bus protocol has been defined (Figure 8):
• Data transfer can be initiated only when the bus is
• During data transfer, the data line must remain sta-
not busy.
ble whenever the clock line is high. Changes in the
data line while the clock line is high can be interpret-
ed as control signals.
1
TCS
DS
TOUT
0-1
0-3
0-1
= DIODE SELECT
= TRICKLE CHARGER SELECT
2
REPEATED IF MORE BYTES
= RESISTOR SELECT
ARE TRANSFERED
3–7
250Ω
2kΩ
4kΩ
R1
R2
R3
SIGNAL FROM RECEIVER
ACKNOWLEDGEMENT
8
V
ACK
BACKUP
9
OR REPEATED
CONDITION
CONDITION
START
STOP