MAX6900ETT+T Maxim Integrated Products, MAX6900ETT+T Datasheet - Page 3

• Manufacturer Part Number: MAX6900ETT+T
• Description: Real Time Clock IC RTC I2C COMPAT atible RTC in a TDFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX6900ETT+T

• Function: Clock, Calendar, Alarm
• Rtc Memory Size: 31 B
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Rtc Bus Interface: Serial
• Package / Case: TDFN EP
• Time Format: HH:MM:SS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AC ELECTRICAL CHARACTERISTICS (continued)
(V
Note 1: All parameters are 100% tested at T
Note 2: I
Note 4: MAX6900 I/O pins do not obstruct the SDA and SCL lines if V
Note 5: Guaranteed by design. Not subject to production testing.
Note 6: All values referred to V
Note 8: C
Note 9: The maximum t
Note 3: I
Note 7: The MAX6900 internally provides a hold time of at least 300ns for the SDA signal (referred to the V
Hold Time After (Repeated)
START Condition (After this
Period, the First Clock Is
Generated)
Repeated START Condition
Setup Time
STOP Condition Setup Time
Data Hold Time (Note 7)
Data Setup Time
SCL Low Period
SCL High Period
Minimum SCL/SDA Rise Time
(Note 8)
Maximum SCL/SDA Rise Time
(Note 8)
Minimum SCL/SDA Fall Time
(Receiving) (Notes 8, 9)
Maximum SCL/SDA Fall Time
(Receiving) (Notes 8, 9)
Minimum SDA Fall Time
(Transmitting) (Notes 8, 9)
Maximum SDA Fall Time
(Transmitting) (Notes 8, 9)
Pulse Width of Spike Suppressed
Capacitive Load for Each
Bus Line
CC
= +2.0V to +5.5V, T
I
in order to bridge the undefined region of the falling edge of SCL.
specified at 250ns. This allows series protection resistors to be connected between the SDA/SCL pins and the SDA/SCL
bus lines without exceeding the maximum specified t
CC
TK
2
C-compatible bus inactive.
B
PARAMETER
is specified with SCL = Logic High (4.7kΩ pullup resistor) and SDA = Logic High (4.7kΩ pullup resistor);
= total capacitance of one bus line in pF.
is specified with SCL = 400kHz and SDA = 400kHz.
_______________________________________________________________________________________
f
A
for the SDA and SCL bus lines is specified at 300ns. The maximum fall time for the SDA output stage t
= T
MIN
IH min
to T
SYMBOL
and V
MAX
t
t
t
t
t
HD:DAT
HD:STA
SU:STA
SU:STO
SU:DAT
t
t
HIGH
LOW
t
C
SP
t
t
t
t
t
t
r
r
f
f
f
f
, unless otherwise noted. Typical values are at V
B
A
IL max
= +25°C. Limits over temperature are guaranteed by design and not production tested.
I
levels.
2
C-Compatible RTC in a TDFN
f
.
CONDITIONS
CC
is switched off.
CC
= +3.3V, T
MIN
100
0.6
0.6
0.6
1.3
0.6
0
A
= +25°C.) (Notes 1, 6)
IH min
0.1C
0.1C
0.1C
20 +
20 +
20 +
TYP
300
300
250
50
B
B
B
of the SCL signal)
MAX
400
0.9
UNITS
f
pF
µs
µs
µs
µs
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
is
3