PI90LVB16LE Pericom Semiconductor, PI90LVB16LE Datasheet - Page 6

• Manufacturer Part Number: PI90LVB16LE
• Description: Clock Drivers & Distribution 1:6 BLVDS to TTL Distribution
• Manufacturer: Pericom Semiconductor

Specifications of PI90LVB16LE

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
Notes:
1. “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. These ratings
2. ESD Rating: ESD qualification is performed per the following: HBM (1.5k
3. Current into device pins are defined as positive. Current out of device pins defined as negative. All voltages are referenced to ground except
4. All typicals are given for: V
5. The VCMR range is reduced for larger VID. Example: If VID=400 mV, then VCMR is 2V to 2.2VAVID up to ⎪V
6. Only one output should be momentarily shorted at a time. Do not exceed package power dissipation rating.
7. C
8. Generator waveform for all tests unless otherwise specified: f = 25 MHz, Zo = 50
10. t
11. t
12. t
13. t
14. t
15. Generator input conditions: t
Switching Characteristics
Differential Driver Timing Requuirements
(Over supply voltage and operating temperature ranges, unless otherwise specificed
9. All device output transition times are based on characterization measurements and are guaranteed by design.
S
t
t
t
t
P
P
t
t
t
t
t
t
y
P
P
t
t
f
are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of
device operation.
pins connected together, all ground pins connected together.
VID, VOD, VTH, and VTL
between the CLKI/O+ and CLKI/O– inputs, with the Common Mode set to V
propagation delay and minimum skew, clock input edge rates should not be slower than 1ns/V; control signals not slower than 3ns/V.
In general, the faster the input edge rate, the better the AC performance,
temperature and V
This parameter is guaranteed by design and characterization.
This specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. t
defined as Max-Min differential propagation delay. This parameter is guaranteed by design and characterization.
specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. t
defined as Max-Min differential propagation delay.
V
S
S
T
T
P
P
P
P
H
L
M
H
L
SKIR
SK2R
SK3R
SK1D
SK2D
m
K
K
L
H
H
Z
L
Z
H
L
H
L
OL
L
A
H
Z
H
L
L
Z
1
2
C
C
b
D
D
includes probe and fixture capacitance.
X
D
D
D
D
D
D
D
D
d r
d r
(max) 0.4V, V
l o
D
D
08-0295
is the difference in receiver propagation delay ⎪t
is the difference in receiver propagation delay between channels in the same device of any outputs switching in the same direction.
part-to-part skew, is the difference in receiver propagation delay between devices of any outputs switching in the same direction.
is the difference in driver propagation delay ⎪t
part-to-part skew, is the difference in driver propagation delay between devices of any outputs switching in the same direction. This
C
C
i D
i D
D
i D
i D
i D
T
T
T
T
M
a r
a r
a r
a r
d r
d r
f i
e f f
e f f
e f f
e f f
e f f
x a
r e f
s n
s n
s n
s n
C
C
m i
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i t i
i t i
L
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t n
t n
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u
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n o
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m
l a i
l a i
l a i
l a i
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CC
N I
N I
OH
S l
T
T
T
T
O
. The propagation delay specification is a device-to-device worst case over process, voltage and temperature.
r P
r P
a P
T
T
m i
m i
m i
m i
o t
o t
(min) 2.7V, Load - 7pF (stray plus probes).
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= +3.3V and T
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o t
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F
e t
- e t
< 1ns, 50% duty cycle, differential (1.10V to 1.35V pk-pk). Output Criteria: 60%/40% duty cycle,
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T
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e r
m i
m i
t -
3
3
r P
r P
–
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= +25°C.
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O /
O /
w
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d r
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PHL
PHL
C
o t
o t
C
L
⎪and is the duty cycle distortion of the CLKI/O outputs.
L
L
i H
⎪ of one device, and is the duty cycle distortion of the output at any given
K
K
o
h g
N I
N I
w
6
o t
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C
C
L
L
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Ω
I
I
, 100pF), Machine Model (250V, 0
O /
O /
CC
/2.
Ω
C
C
C
C
, t
R
F
F
F
V
R
F
g i
g i
g i
g i
L
L
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r
N I
= 1ns, t
r u
r u
r u
r u
=
=
=
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=
=
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=
(7,8)
s e
s e
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o
1
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1
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n
0
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p 5
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p 5
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6
8
6
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V
5 .
5 .
t i
F
F
F
F
&
&
&
f
Ω
Ω
o i
o t
&
= 1ns (10%–90%). To ensure fastest
s n
7
9
7
V
1 1
C
Clock Buffer/Bus Transceiver
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M
1
1
1
2
2
0
0
0 0
0 .
0 .
0 .
0 .
2 .
2 .
. n i
Ω
), IEC 1000-4-2. All V
CC
3V Bus LVDS 1-to-6
-0V⎪ may be applied
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. 0
1
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1
1
2
2
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8 .
8 .
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5 3
5 .
3 .
) 1 (
PI90LVB16
PS8536C
M
T
SK2D
. 0
. 0
6
2
2
4
4
2
2
4
3
B
0 0
a
5 .
5 .
3 .
2 .
2 .
5 6
5 6
6 .
6 .
6 .
D
. x
SK3R
is
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M
CC
11/11/08
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