M41T256YMT7 STMicroelectronics, M41T256YMT7 Datasheet - Page 15

• Manufacturer Part Number: M41T256YMT7
• Description: Real Time Clock Serial 256K (32Kx8)
• Manufacturer: STMicroelectronics

Specifications of M41T256YMT7

• Function: Clock, Calendar
• Rtc Memory Size: 32768 B
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: - 25 C
• Mounting Style: SMD/SMT
• Rtc Bus Interface: Serial
• Package / Case: SO-44
• Time Format: HH:MM:SS:hh
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.3
Figure 10. Write mode sequence
2.4
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
Write mode
In this mode the master transmitter transmits to the M41T256Y slave receiver. Bus protocol
is shown in
'0' (R/W=0) is placed on the bus and indicates to the addressed device that byte addresses
A(0) and A(1) will follow and is to be written to the on-chip address pointer (MSB of address
byte A(0) is a “Don’t care”).
The data byte to be written to the memory is strobed in next and the internal address pointer
is incremented to the next memory location within the RAM on the reception of an
acknowledge bit. The M41T256Y slave receiver will send an acknowledge bit to the master
transmitter after it has received the slave address (see
it has received each address byte.
Data retention mode
With valid V
WRITE cycles. Should the supply voltage decay, the M41T256Y will automatically deselect,
write protecting itself when V
accomplished by internally inhibiting access to the clock registers. At this time, the reset pin
(RST) is driven active and will remain active until V
falls below the battery back-up switchover voltage (V
V
attached battery supply.
All outputs become high impedance. On power up, when V
write protection continues for t
Figure 14 on page
For a further more detailed review of lifetime calculations, please see Application Note
AN1012.
CC
pin to the external battery and the clock registers and SRAM are maintained from the
S
Figure 10 on page
CC
ADDRESS
SLAVE
applied, the M41T256Y can be accessed as described above with READ or
25).
ADDRESS (0)
CC
BYTE
REC
15. Following the START condition and slave address, a logic
falls between V
. The RST signal also remains active during this time (see
ADDRESS (1)
BYTE
PFD
CC
(max) and V
SO
returns to nominal levels. When V
Figure 7 on page
DATA n
), power input is switched from the
CC
returns to a nominal value,
PFD
DATA n+X
(min). This is
13) and again after
AI04761
P
15/30
CC