DS34S102GN Maxim Integrated Products, DS34S102GN Datasheet - Page 10

• Manufacturer Part Number: DS34S102GN
• Description: Communication ICs - Various Dual TDM-Over-Packet Transport Devices A
• Manufacturer: Maxim Integrated Products

7 Pin Descriptions
7.1 Short Pin Descriptions
Table 7-1. Short Pin Descriptions
Rev: 032609
____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
PIN NAME
TDM Interface
TDMn_ACLK
TDMn_TCLK
TDMn_TX
TDMn_TX_SYNC
TDMn_TX_MF_CD
TDMn_TSIG_CTS
TDMn_RCLK
TDMn_RX
TDMn_RX_SYNC
TDMn_RSIG_RTS
SDRAM Interface
SD_CLK
SD_D[31:0]
SD_DQM[3:0]
SD_A[11:0]
SD_BA[1:0]
SD_CS_N
SD_WE_N
SD_RAS_N
SD_CAS_N
Ethernet PHY Interface (MII/RMII/SSMII)
CLK_MII_TX
CLK_SSMII_TX
MII_TXD[3:0]
MII_TX_EN
MII_TX_ERR
CLK_MII_RX
MII_RXD[3:0]
MII_RX_DV
MII_RX_ERR
MII_COL
MII_CRS
MDC
MDIO
Global Clocks
CLK_SYS_S
CLK_SYS
CLK_CMN
CLK_HIGH
CPU Interface
H_CPU_SPI_N
DAT_32_16_N
H_D[31:1]
H_D[0] / SPI_MISO
H_AD[24:1]
H_CS_N
H_R_W_N / SPI_CP
H_WR_BE0_N / SPI_CLK
H_WR_BE1_N / SPI_MOSI
TYPE
IOpd
IOpu
Ipu
Ipd
Ipu
Ipu
Ipd
Ipu
Ipu
Ipu
IO
IO
IO
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
PIN DESCRIPTION
TDMoP Recovered Clock Output
TDMoP Transmit Clock Input (here transmit means “away from Ethernet MII”)
TDMoP Transmit Data Output
TDMoP Transmit Frame Sync Input
TDMoP Transmit Multiframe Sync Input or Carrier Detect Output
TDMoP Transmit Signaling Output or Clear to Send Output
TDMoP Receive Clock Input (here receive means “toward Ethernet MII”)
TDMoP Receive Data Input
TDMoP Receive Frame/Multiframe Sync Input
TDMoP Receive Signaling Input or Request To Send Input
SDRAM Clock
SDRAM Data Bus
SDRAM Byte Enable Mask
SDRAM Address Bus
SDRAM Bank Select Outputs
SDRAM Chip Select (Active Low)
SDRAM Write Enable (Active Low)
SDRAM Row Address Strobe (Active Low)
SDRAM Column Address Strobe (Active Low)
MII Transmit Clock Input
SSMII Transmit Clock Output
MII Transmit Data Outputs
MII Transmit Enable Output
MII Transmit Error Output
MII Receive Clock Input
MII Receive Data Inputs
MII Receive Data Valid Input
MII Receive Error Input
MII Collision Input
MII Carrier Sense Input
PHY Management Clock Output
PHY Management Data Input/Output
System Clock Selection Input
System Clock Input: 25, 50 or 75MHz
Common Clock Input (for common clock mode also known as differential mode)
Clock High Input (for adaptive clock recovery machines and E1/T1 master clocks)
Host Bus Interface (1=Parallel Bus, 0=SPI Bus)
Data Bus Width (1=32-bit , 0=16-bit)
Host Data Bus
Host Data LSb or SPI Data Output
Host Address Bus
Host Chip Select (Active Low)
Host Read/Write Control or SPI Clock Phase
Host Write Enable Byte 0 (Active Low) or SPI Clock
Host Write Enable Byte 1 (Active Low) or SPI Data Input
10 of 13