LX128V-32FN208C Lattice, LX128V-32FN208C Datasheet - Page 37

• Manufacturer Part Number: LX128V-32FN208C
• Description: Analog & Digital Crosspoint ICs 128 I/O Switch Matrix, 3.3V, SERDES, 3.2ns, Pb-Free
• Manufacturer: Lattice

Specifications of LX128V-32FN208C

• Maximum Dual Supply Voltage: 3.6 V
• Minimum Dual Supply Voltage: 3 V
• Mounting Style: SMD/SMT
• Number Of Arrays: 1
• Operating Supply Voltage: 3.3 V
• Supply Type: Triple
• Configuration: 128 x 128
• Package / Case: FPBGA-208
• Data Rate: 21 Gbps
• Input Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Output Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Maximum Operating Temperature: + 90 C
• Minimum Operating Temperature: 0 C
• Product: Digital Crosspoint
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ispGDX2V/B/C, ispGDX2EV/EB/EC Internal Timing Parameters
Lattice Semiconductor
t
t
t
t
t
t
t
t
Register/Latch Delays, Input Paths
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
OE Paths
t
t
t
t
t
t
t
t
t
t
t
OPLGOi
OPLHi
OPLPDi
OPLSi
OPLSi_PT
OPSi
OPSi_PT
OPSRPWi
IPASROi
IPASRRi
IPBYPASS
IPCEHi
IPCESi
IPCESi_PT
IPCOi
IPHi
IPLGOi
IPLHi
IPLPDi
IPLSi
IPLSi_PT
IPSi
IPSi_PT
IPSRPWi
OEASROi
OEASRRi
OEBYPASS
OECEHi
OECESi
OECESi_PT
OECOi
OEHi
OELGOi
OELHi
OELPDi
Parameter
Latch Gate to Output Delay
Latch Hold Time
Latch Propagation Delay (Transparent
Mode)
Latch Setup Time (Global Gate)
Latch Setup Time (Product Term Gate)
Register Setup Time (Global Clock)
Register Setup Time (Product Term Clock)
Asynchronous Set/Reset Pulse Width
Asynchronous Set/Reset to Output
Asynchronous Set/Reset Recovery
Register/Latch Bypass Delay
Register Clock Enable Hold Time
Register Clock Enable Setup Time
(Global Clock Enable)
Register Clock Enable Setup Time
(Product Term Clock Enable)
Register Clock to Output Delay
Register Hold Time
Latch Gate to Output Delay
Latch Hold Time
Latch Propagation Delay (Transparent
Mode)
Latch Setup Time (Global Term)
Latch Setup Time (Product Term Gate)
Register Setup Time (Global Clock)
Register Setup Time (Product Term Clock)
Asynchronous Set/Reset Pulse Width
Asynchronous Set/Reset to Output
Asynchronous Set/Reset Recovery
Register/Latch Bypass Delay
Register Clock Enable Hold Time
Register Clock Enable Setup Time (Global
Clock Enable)
Register Clock Enable Setup Time
(Product Term Clock Enable)
Register Clock to Output Delay
Register Hold Time
Latch Gate to Output Delay
Latch Hold Time
Latch Propagation Delay (Transparent
Mode)
Description
Over Recommended Operating Conditions
34
Min.
0.80
1.20
1.00
1.20
1.00
1.30
1.10
1.10
0.00
0.00
1.50
1.50
1.50
1.50
1.30
1.20
1.50
0.40
0.40
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-3
Max.
1.00
0.30
2.50
1.00
2.50
0.00
0.80
1.00
0.30
2.50
2.50
2.50
0.00
1.30
1.60
0.30
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Min.
0.80
1.20
1.00
1.20
1.00
1.30
1.10
1.10
0.00
0.00
1.50
1.50
1.50
1.50
1.30
1.20
1.50
0.40
0.40
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-32
Max.
1.00
0.30
2.50
1.00
2.50
0.00
1.00
1.00
0.30
2.50
2.50
2.50
0.00
1.30
1.60
0.30
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ispGDX2 Family Data Sheet
Min.
0.80
1.20
1.00
1.20
1.00
1.30
1.10
1.10
0.00
0.00
1.50
1.50
1.50
1.50
0.80
1.20
2.10
0.40
0.40
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-35
Max.
1.00
0.30
2.50
1.70
2.50
0.00
1.00
1.00
0.30
2.50
2.50
2.50
0.00
1.60
1.60
0.30
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
(Continued)
Min.
1.33
2.00
1.67
2.00
1.67
2.17
1.83
1.83
0.00
0.00
2.50
2.50
2.50
2.50
1.33
2.00
3.50
0.67
0.67
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-5
Max.
1.67
0.50
4.17
2.83
4.17
0.00
1.67
1.67
0.50
4.17
4.17
4.17
0.00
2.67
2.67
0.50
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns