LX128EV-5FN208I Lattice, LX128EV-5FN208I Datasheet - Page 8

• Manufacturer Part Number: LX128EV-5FN208I
• Description: Analog & Digital Crosspoint ICs E-Series, 128 I/O Switch Matrix, 3.3V, 5ns, IND, Pb-Free
• Manufacturer: Lattice

Specifications of LX128EV-5FN208I

• Maximum Dual Supply Voltage: 3.6 V
• Minimum Dual Supply Voltage: 3 V
• Mounting Style: SMD/SMT
• Number Of Arrays: 1
• Operating Supply Voltage: 3.3 V
• Supply Type: Triple
• Configuration: 128 x 128
• Package / Case: FPBGA-208
• Data Rate: 21 Gbps
• Input Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Output Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Product: Digital Crosspoint
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 2. GDX Block
The output register of the MRB has a built-in bi-directional shift register capability. Each output register correspond-
ing to MRB “n”, receives data output from its two adjacent MRBs, MRB (n-1) and MRB (n+1), to provide shift regis-
ter capability. Like the output register, each input register of the MRB has built-in shift register capability. Each input
register can receive data from its two adjacent MRB input registers, to provide bi-directional shift register capability.
The chaining crosses GDX Block boundaries. The chain of input registers and the chain of output registers can be
combined as one shift register via the GRP.
GRP
32 bits
4 bits
4 bits
4 bits
4 bits
16 bits
16 bits
16 bits
4
4
4
Control
8
Select
8
8
8
MUX
8
2
2
2
8
8
8
8
2
2
2
2
GDX Block
Control Array
5
MRBs 12-15
MUX and Register
MUX and Register
MUX and Register
MUX and Register
MRBs 8-11
MRBs 4-7
Nibble 0
Nibble 1
Nibble 2
Nibble 3
Block (MRB)
Block (MRB)
Block (MRB)
Block (MRB)
0
1
2
3
ispGDX2 Family Data Sheet
sysIO Bank
OE
IN
OUT
OE
IN
OUT
OE
IN
OUT
OE
IN
OUT
OE
IN
OUT
OE
IN
OUT
OE
IN
OUT