LX256V-5FN484C Lattice, LX256V-5FN484C Datasheet - Page 44

• Manufacturer Part Number: LX256V-5FN484C
• Description: Analog & Digital Crosspoint ICs 256 I/O Switch Matrix, 3.3V, SERDES, 5ns, Pb-Free
• Manufacturer: Lattice

Specifications of LX256V-5FN484C

• Maximum Dual Supply Voltage: 3.6 V
• Minimum Dual Supply Voltage: 3 V
• Mounting Style: SMD/SMT
• Number Of Arrays: 1
• Operating Supply Voltage: 3.3 V
• Supply Type: Triple
• Configuration: 256 x 256
• Package / Case: FPBGA-484
• Data Rate: 38 Gbps
• Input Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Output Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Maximum Operating Temperature: + 90 C
• Minimum Operating Temperature: 0 C
• Product: Digital Crosspoint
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Deserializer Timing
Lock-in Timing
f
eo
ber
t
t
t
1. Eye opening based on jitter frequency of 100KHz.
2. Lower frequency operation assumes maximum eye closure of 800ps.
3. Internal timing for reference only.
DSIN
HSIOUTVALIDPRE
HSIOUTVALIDPOST
DSIN
SIN
Symbol
SIN Frequency Deviation from REFCLK
SIN Eye Opening Tolerance
Bit Error Rate
RXD, SYDT Valid Time Before RECCLK Fall-
ing Edge
RXD, SYDT Valid Time
After RECCLK Falling Edge
Bit 0 of SIN Delay to RXD Valid at RECCLK
Falling edge
RXD(0:9)
SYDT
CDRX_SS LOCK-IN (DE-SKEW) TIMING
SIN
RXD(0:7)
CAL
SYDT
SIN
CDR_10B12B LOCK-IN TIMING
Description
t
SUSYNC
MIN. 1100 LS CYCLE
TRAINING SEQUENCE
MIN. 1200 SYNCPAT
1024 SYNCPAT
SYNCPAT
SYNCPAT
41
10B12B
8B10B/
Mode
All
All
All
All
All
SS MODE DATA TRANSFER
t
HDSYNC
DATA (PARALLEL)
Conditions
Notes 1, 2
DATA (SERIAL )
DATA (PARALLEL)
DATA (SERIAL )
Note 3
Note 3
ispGDX2 Family Data Sheet
t
t
RCP
RCP
1.5 t
4.5Bt + 2
Min.
-100
0.45
/2 - 0.7
/2 - 0.7
RCP
+
4.5Bt + 10
1.5 t
Max.
10
100
RCP
-12
+
Units
UIPP
ppm
Bits
ns
ns
ns