ispGDX160V-7Q208 Lattice, ispGDX160V-7Q208 Datasheet - Page 2

• Manufacturer Part Number: ispGDX160V-7Q208
• Description: Analog & Digital Crosspoint ICs USE ispGDX2
• Manufacturer: Lattice

Specifications of ispGDX160V-7Q208

• Maximum Dual Supply Voltage: 3.6 V
• Minimum Dual Supply Voltage: 2.3 V, 3 V
• Mounting Style: SMD/SMT
• Number Of Arrays: 1
• Operating Supply Voltage: 2.5 V, 3.3 V
• Supply Type: Dual
• Configuration: Programmable
• Package / Case: PQFP-208
• Input Level: TTL
• Output Level: TTL
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Product: Digital Crosspoint
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

• IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL
• HIGH PERFORMANCE E
• ispGDXV OFFERS THE FOLLOWING ADVANTAGES
• FLEXIBLE ARCHITECTURE
• LEAD-FREE PACKAGE OPTIONS
* “VA” Version Only
Copyright © 2004 Lattice Semiconductor Corporation. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein
are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. [phone]; 1-800-LATTICE; FAX [phone]; http://www.latticesemi.com
gdx160va_06
Features
CROSSPOINT FAMILY
— Advanced Architecture Addresses Programmable
— “Any Input to Any Output” Routing
— Fixed HIGH or LOW Output Option for Jumper/DIP
— Space-Saving PQFP and BGA Packaging
— Dedicated IEEE 1149.1-Compliant Boundary Scan
— 3.3V Core Power Supply
— 3.5ns Input-to-Output/3.5ns Clock-to-Output Delay*
— 250MHz Maximum Clock Frequency*
— TTL/3.3V/2.5V Compatible Input Thresholds and
— Low-Power: 16.5mA Quiescent Icc*
— 24mA I
— PCI Compatible Drive Capability*
— Schmitt Trigger Inputs for Noise Immunity
— Electrically Erasable and Reprogrammable
— Non-Volatile E
— 3.3V In-System Programmable Using Boundary Scan
— Change Interconnects in Seconds
— Combinatorial/Latched/Registered Inputs or Outputs
— Individual I/O Tri-state Control with Polarity Control
— Dedicated Clock/Clock Enable Input Pins (four) or
— Single Level 4:1 Dynamic Path Selection (Tpd = 3.5ns)
— Programmable Wide-MUX Cascade Feature
— Programmable Pull-ups, Bus Hold Latch and Open
— Outputs Tri-state During Power-up (“Live Insertion”
PCB Interconnect, Bus Interface Integration and
Jumper/Switch Replacement
Switch Emulation
Test
Output Levels (Individually Programmable)*
Control Option
Test Access Port (TAP)
Programmable Clocks/Clock Enables from I/O Pins
(40)
Supports up to 16:1 MUX
Drain on I/O Pins
Friendly)
OL
Drive with Programmable Slew Rate
2
CMOS Technology
2
CMOS
®
TECHNOLOGY
1
The ispGDXV/VA architecture provides a family of fast,
flexible programmable devices to address a variety of
system-level digital signal routing and interface require-
ments including:
The devices feature fast operation, with input-to-output
signal delays (Tpd) of 3.5ns and clock-to-output delays of
3.5ns.
The architecture of the devices consists of a series of
programmable I/O cells interconnected by a Global Rout-
ing Pool (GRP). All I/O pin inputs enter the GRP directly
or are registered or latched so they can be routed to the
required I/O outputs. I/O pin inputs are defined as four
sets (A,B,C,D) which have access to the four MUX inputs
Functional Block Diagram
Description
• Multi-Port Multiprocessor Interfaces
• Wide Data and Address Bus Multiplexing
• Programmable Control Signal Routing
• Board-Level PCB Signal Routing for Prototyping or
Boundary
(e.g. 16:1 High-Speed Bus MUX)
(e.g. Interrupts, DMAREQs, etc.)
Programmable Bus Interfaces
Control
Scan
ispGDX
Cells
I/O
3.3V Generic Digital Crosspoint
Global Routing
In-System Programmable
I/O Pins D
I/O Pins B
(GRP)
Pool
®
160V/VA
Cells
I/O
August 2004
Control
ISP