CS8900A-CQ3ZR Cirrus Logic Inc, CS8900A-CQ3ZR Datasheet - Page 92

• Manufacturer Part Number: CS8900A-CQ3ZR
• Description: Ethernet ICs IC 10Mbps Ethernet Controller 3.3V
• Manufacturer: Cirrus Logic Inc

Specifications of CS8900A-CQ3ZR

• Ethernet Connection Type: 10Base- 2, 10Base- 5, 10Base- F, 10Base- T
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE 802.3
• Data Rate: 10 Mbps
• Maximum Operating Temperature: + 70 C
• Package / Case: LQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Note that when in DMA mode, reading the con-
tents of the RxEvent register will return 0000h.
Status information should be obtained from
the DMA buffer.
5.3.5 Committing Buffer Space to a
DMAed Frame
Although a receive frame may occupy space in
the host memory's circular DMA buffer, the
CS8900A's Memory Manager does not com-
mit the buffer space to the receive frame until
the entire frame has been transferred and the
host learns of the frame's existence by reading
the Frame Count register (PacketPage base +
0028h).
When the CS8900A commits DMA buffer
space to a particular DMAed receive frame
(termed a committed received frame), no data
from subsequent frames can be written to that
buffer space until the committed received
frame is freed from commitment. (The commit-
ted received frame may or may not have been
received error free.)
A committed DMAed receive frame is freed
from commitment by any one of the following
conditions:
1) The host rereads the DMA Frame Count
2) New frames have been transferred via
3) The host issues a Reset-DMA command
5.3.6 DMA Buffer Organization
When DMA is used to transfer receive frames,
the DMA Start-of-Frame register (PacketPage
Base + 0026h) defines the offset from the
92
register (PacketPage base + 0028h).
DMA, and the host reads the BufEvent reg-
ister (either directly or from the ISQ) and
sees that the RxDMAFrame bit is set (this
condition is termed an "implied Skip").
by setting the ResetRxDMA bit (Register
17, BusCTL, Bit 6).
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DMA base to the start of the most recently
transferred received frame. Frames stored in
the DMA buffer are transferred as words and
maintain double-word (32-bit) alignment. Un-
filled memory space between successive
frames stored in the DMA buffer may result
from double-word alignment. These "holes"
may be 1, 2, or 3 bytes, depending on the
length of the frame preceding the hole.
5.3.7 RxDMAFrame Bit
The RxDMAFrame bit (Register C, BufEvent,
bit 7) is controlled by the CS8900A and is set
whenever the value in the DMA Frame Count
register is non-zero. The host cannot clear Rx-
DMAFrame by reading the BufEvent register
(Register C). Table 28 summarizes the criteria
used to set and clear RxDMAFrame.
5.3.8 Receive DMA Example Without
Wrap-Around
Figure 24 shows three frames stored in host
memory by DMA without wrap-around.
5.3.9 Receive DMA Operation for RxDMA-
Only Mode
In an RxDMAOnly mode, a system DMA
moves all the received frames from the on-
chip memory to an external 16- or 64-Kbyte
buffer memory. The received frame must have
passed the destination address filter, and must
To set RxD-
MAFrame
To Clear
RxDMA-
Frame
The RxDMAFrame
bit is set whenever
the DMA Frame
Count register
(PacketPage base +
0028h) transitions to
non-zero.
The DMA Frame
Count is zero.
Table 28. RxDMAFrame Bit
Crystal LAN™ Ethernet Controller
Transfer Mode
Non-Stream
The RxDMAFrame
bit is set at the end
of a Stream Transfer
cycle.
The DMA Frame
Count is zero.
Stream Transfer
Section 5.5)
Mode (see
CS8900A
DS271F5