CS8900A-IQ3ZR Cirrus Logic Inc, CS8900A-IQ3ZR Datasheet - Page 66

• Manufacturer Part Number: CS8900A-IQ3ZR
• Description: Ethernet ICs IC 10Mbps Ethernet Controller 3.3V
• Manufacturer: Cirrus Logic Inc

Specifications of CS8900A-IQ3ZR

• Ethernet Connection Type: 10Base- 2, 10Base- 5, 10Base- F, 10Base- T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE 802.3
• Data Rate: 10 Mbps
• Maximum Operating Temperature: + 85 C
• Package / Case: LQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ResetRxDMA
DMAextend
UseSA
MemoryE
DMABurst
IOCHRDYE
RxDMAsize
EnableRQ
After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state. If an EEPROM
is found, then the register's initial value may be set by the EEPROM. See Section 3.3 on page 19.
Reset value is: 0000 0000 0001 0111
4.4.21 Register 18: Bus Status
(BusST, Read-only, Address: PacketPage base + 0138h)
BusST describes the status of the current transmit operation.
011000
66
TxBidErr
7
F
host sets this bit, the CS8900A does the following:
1.Terminates the current receive DMA activity, if any.
2.Clears all internal receive buffers.
3.Zeroes the RxDMA offset pointer.
IOR
transfer mode DMA. Normal operation is demand mode DMA in which DMACKx cannot deas-
sert until after DMARQx deasserts, i.e. until a full ethernet frame is transferred. Single transfer
mode allows DMACKx to deassert between each DMA read.
CS8900A's assigned Memory base address and the CHIPSEL pin is low (internal address de-
code).
see Section 4.9 on page 73.
For MEMCS16 pin to be enabled, the CS8900A must be in Memory Mode with the MemoryE
bit (Register 17, BusCTL, Bit A) set.
I/O Mode is always enabled.
transferred from the CS8900A to host memory. When set, each DMA access is limited to 28us,
after which time the CS8900A gives up the bus for 1.3us before making a new DMA request.
pedance. This allows external pull-up to force the output high. When clear, the CS8900A drives
IOCHRDY low to request additional time during I/O Read and Memory Read cycles. IOCHRDY
does not affect I/O Write, Memory Write, nor DMA Read.
DMA buffer size is 64 Kbytes. When clear, it is 16 Kbytes.
(Section 5.1). When cleared, the CS8900A will not generate any interrupts.
When set, the RxDMA offset pointer at PacketPage base + 0026h is reset to zero. When the
When set, DMARQx goes inactive on the falling edge of IOR
When set, the MEMCS16 pin goes low whenever the address on SA bus [12..19] match the
When set, the CS8900A may operate in Memory Mode. When clear, Memory Mode is disabled.
When clear, the CS8900A performs continuous DMA until the receive frame is completely
When set, the CS8900A does not use the IOCHRDY output pin, and the pin is always high-im-
This bit determines the size of the receive DMA buffer (located in host memory). When set, the
When set, the CS8900A will generate an interrupt in response to an interrupt event
These bits provide an internal address used by the CS8900A to identify this as the Bus Status
E
When clear, MEMCS16 is driven low whenever CHIPSEL goes low. (external address decode).
6
N
-1
. See Switching Characteristics, DMA Read, t
D
5
CIRRUS LOGIC PRODUCT DATASHEET
C
4
B
3
011000
DMAR5
Crystal LAN™ Ethernet Controller
A
2
. Setting this bit also enables single
N
instead of the rising edge of
1
9
Rdy4Tx NOW
CS8900A
DS271F5
0
8