LAN9215-MZP SMSC, LAN9215-MZP Datasheet - Page 81
LAN9215-MZP
Manufacturer Part Number
LAN9215-MZP
Description
Ethernet ICs 16-BIT NON-PCI 10/100 ETHERNET CTRL
Manufacturer
SMSC
Type
Single Chip MAC and PHY Controllerr
Datasheet
1.LAN9215-MZP.pdf
(143 pages)
Specifications of LAN9215-MZP
Ethernet Connection Type
10 Base-T, 100 Base-TX
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Product
Ethernet Controllers
Number Of Transceivers
1
Standard Supported
802.3, 802.3u
Data Rate
10 MB, 100 MB
Supply Voltage (max)
3.3 V
Supply Voltage (min)
0 V
Supply Current (max)
69 mA
Maximum Operating Temperature
+ 70 C
Package / Case
TQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LAN9215-MZP
Manufacturer:
SMSC
Quantity:
17 600
Part Number:
LAN9215-MZP
Manufacturer:
SMSC
Quantity:
20 000
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16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support
Datasheet
SMSC LAN9215
5.3.5
5.3.6
31-24
23-16
BITS
BITS
31:0
15-8
7-0
Byte Test
TX Data Available Level. The value in this field sets the level, in number
of 64 Byte blocks, at which the TX FIFO Available interrupt (TFDA) will be
generated. When the TX data FIFO free space is greater than this value a
TX FIFO Available interrupt (TDFA) will be generated.
TX Status Level. The value in this field sets the level, in number of
DWORDs, at which the TX Status FIFO Level interrupt (TSFL) will be
generated. When the TX Status FIFO used space is greater than this value
an TX Status FIFO Level interrupt (TSFL) will be generated.
Reserved
RX Status Level. The value in this field sets the level, in number of
DWORDs, at which the RX Status FIFO Level interrupt (RSFL) will be
generated. When the RX Status FIFO used space is greater than this value
an RX Status FIFO Level interrupt (RSFL) will be generated.
BYTE_TEST—Byte Order Test Register
This register can be used to determine the byte ordering of the current configuration
FIFO_INT—FIFO Level Interrupts
This register configures the limits where the FIFO Controllers will generate system interrupts.
Offset:
Offset:
DESCRIPTION
DESCRIPTION
64h
68h
DATASHEET
81
Size:
Size:
32 bits
32 bits
TYPE
TYPE
R/W
R/W
R/W
RO
RO
Revision 2.7 (03-15-10)
87654321h
DEFAULT
DEFAULT
48h
00h
00h
-
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