LAN8700IC-AEZG-TR SMSC, LAN8700IC-AEZG-TR Datasheet - Page 51

• Manufacturer Part Number: LAN8700IC-AEZG-TR
• Description: Ethernet ICs Hi Perform Ethernet PHY
• Manufacturer: SMSC
• Type: MII/RMII Ethernet Transceiverr

Specifications of LAN8700IC-AEZG-TR

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Transceivers
• Number Of Transceivers: 1
• Standard Supported: 802.3ab
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 1.8 V
• Supply Current (max): 39 mA, 81.6 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: QFN-36
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR
Datasheet
SMSC LAN8700/LAN8700i
5.4.6
5.4.7
the PHY powers-up. It automatically resets itself into the state it had prior to power-down, and asserts
the nINT interrupt if the ENERGYON interrupt is enabled.
to activate ENERGYON may be lost.
When 17.13 is low, energy detect power-down is disabled.
Reset
The PHY has 3 reset sources:
Hardware reset (HWRST): connected to the nRST input. At power up, nRST must not go high until
after the VDDIO and VDD_CORE supplies are stable, as shown in
To initiate a hardware reset, nRST must be held LOW for at least 100 us to ensure that the Phy is
properly reset, as shown in
During a Hardware reset, an external clock must be supplied to the CLKIN signal.
Software (SW) reset: Activated by writing register 0, bit 15 high. This signal is self- clearing. After the
register-write, internal logic extends the reset by 256µs to allow PLL-stabilization before releasing the
logic from reset.
The IEEE 802.3u standard, clause 22 (22.2.4.1.1) states that the reset process should be completed
within 0.5s from the setting of this bit.
Power-Down reset: Automatically activated when the PHY comes out of power-down mode. The
internal power-down reset is extended by 256µs after exiting the power-down mode to allow the PLLs
to stabilize before the logic is released from reset.
These 3 reset sources are combined together in the digital block to create the internal “general reset”,
SYSRST, which is an asynchronous reset and is active HIGH. This SYSRST directly drives the PCS,
DSP and MII blocks. It is also input to the Central Bias block in order to generate a short reset for the
PLLs.
The SMI mechanism and registers are reset only by the Hardware and Software resets. During Power-
Down, the SMI registers are not reset. Note that some SMI register bits are not cleared by Software
reset – these are marked “NASR” in the register tables.
For the first 16us after coming out of reset, the MII will run at 2.5 MHz. After that it will switch to 25
MHz if auto-negotiation is enabled.
LED Description
The PHY provides four LED signals. These provide a convenient means to determine the mode of
operation of the Phy. All LED signals are either active high or active low.
VDD33 Starts
3.3V
1.8V
0V
Figure 5.1 Reset Timing Diagram
VDD_CORE Starts
Figure
DATASHEET
6.10.
®
51
Technology in a Small Footprint
nRST Released
The first and possibly the second packet
Figure
5.1.
Revision 2.2 (12-04-09)