LPC47M112-MW SMSC, LPC47M112-MW Datasheet - Page 26
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LPC47M112-MW
Manufacturer Part Number
LPC47M112-MW
Description
Ethernet ICs Enhanced Super I/O Cntrl LPC Interface
Manufacturer
SMSC
Datasheet
1.LPC47M112-MW.pdf
(204 pages)
Specifications of LPC47M112-MW
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Enhanced Super I/O Controller with LPC Interface
Datasheet
BIT 2 nINDEX
Active low status of the INDEX disk interface input.
BIT 3 HEAD SELECT
Active high status of the HDSEL disk interface input. A logic "1" selects side 1 and a logic "0" selects side 0.
BIT 4 nTRACK 0
Active low status of the TRK0 disk interface input.
BIT 5 STEP
Active high status of the STEP output disk interface output pin.
BIT 6 nDRV2
This function is not supported. This bit is always read as “1”.
BIT 7 INTERRUPT PENDING
Active high bit indicating the state of the Floppy Disk Interrupt output.
PS/2 Model 30 Mode
BIT 0 nDIRECTION
Active low status indicating the direction of head movement. A logic "0" indicates inward direction; a logic "1" indicates
outward direction.
BIT 1 WRITE PROTECT
Active high status of the WRITE PROTECT disk interface input. A logic "1" indicates that the disk is write protected.
BIT 2 INDEX
Active high status of the INDEX disk interface input.
BIT 3 nHEAD SELECT
Active low status of the HDSEL disk interface input. A logic "0" selects side 1 and a logic "1" selects side 0.
BIT 4 TRACK 0
Active high status of the TRK0 disk interface input.
BIT 5 STEP
Active high status of the latched STEP disk interface output pin. This bit is latched with the STEP output going active,
and is cleared with a read from the DIR register, or with a hardware or software reset.
BIT 6 DMA REQUEST
Active high status of the DMA request pending.
BIT 7 INTERRUPT PENDING
Active high bit indicating the state of the Floppy Disk Interrupt.
SMSC DS – LPC47M112
RESET
COND.
PENDING
INT
7
0
DRQ
DATASHEET
6
0
STEP
F/F
5
0
Page 26
TRK0 nHDSEL
N/A
4
3
1
INDX
N/A
2
N/A
WP
1
nDIR
0
1
Rev. 02-16-07
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