LAN9500AI-ABZJ SMSC, LAN9500AI-ABZJ Datasheet - Page 10

• Manufacturer Part Number: LAN9500AI-ABZJ
• Description: Ethernet ICs Hi-Speed USB 2.0 10/100 Ethernet CTRL
• Manufacturer: SMSC

Specifications of LAN9500AI-ABZJ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 1.0 (05-17-10)
2.1.2
2.1.3
2.1.4
2.1.5
USB
The USB portion of the LAN950x integrates a Hi-Speed USB 2.0 device controller and USB PHY.
The USB device controller contains a USB low-level protocol interpreter which implements the USB
bus protocol, packet generation/extraction, PID/Device ID parsing, and CRC coding/decoding, with
autonomous error handling. The USB device controller is capable of operating in USB 2.0 Hi-Speed
and Full-Speed compliant modes and contains autonomous protocol handling functions such as
handling of suspend/resume/reset conditions, remote wakeup, and stall condition clearing on Setup
packets. The USB device controller also autonomously handles error conditions such as retry for CRC
and data toggle errors, and generates NYET, STALL, ACK and NACK handshake responses,
depending on the endpoint buffer status.
The LAN950x implements four USB endpoints: Control, Interrupt, Bulk-in, and Bulk-out. The Bulk-in
and Bulk-out Endpoints allow for Ethernet reception and transmission respectively. Implementation of
vendor-specific commands allows for efficient statistics gathering and access to the device’s system
control and status registers.
FIFO Controller
The FIFO controller uses an internal SRAM to buffer RX and TX traffic. Bulk-out packets from the USB
controller are directly stored into the TX buffer. Ethernet Frames are directly stored into the RX buffer
and become the basis for bulk-in packets.
Ethernet
The LAN950x integrates an IEEE 802.3 PHY for twisted pair Ethernet applications and a 10/100
Ethernet Media Access Controller (MAC).
The PHY can be configured for either 100 Mbps (100BASE-TX) or 10 Mbps (10BASE-T) Ethernet
operation in either full- or half-duplex configurations and includes auto-negotiation, auto-polarity
correction, and Auto-MDIX. Minimal external components are required for the utilization of the
Integrated PHY.
Optionally, an external PHY may be used via the MII (Media Independent Interface) port, effectively
bypassing the internal PHY. This option allows support for HomePNA and HomePlug applications.
The Ethernet MAC/PHY supports numerous power management wakeup features, including “Magic
Packet”, “Wake on LAN”, and “Link Status Change”. Eight wakeup frame filters are provided by
LAN9500A/LAN9500Ai, while LAN9500/LAN9500i support four.
Power Management
The LAN950x features four
SUSPEND2, and SUSPEND3. These modes allow the application to select the ideal balance of remote
wakeup functionality and power consumption.
Note 2.1
SUSPEND0: Supports GPIO, “Wake On LAN”, and “Magic Packet” remote wakeup events. This
suspend state reduces power by stopping the clocks of the MAC and other internal modules.
SUSPEND1: Supports GPIO and “Link Status Change” for remote wakeup events. This suspend
state consumes less power than SUSPEND0.
SUSPEND2: Supports only GPIO assertion for a remote wakeup event. This is the default suspend
mode for the device.
SUSPEND3:
is a received frame passing certain filtering constraints independent of those imposed on “Wake
On LAN” and “Magic Packet” frames. This suspend state consumes power at a level similar to the
NORMAL state, however, it allows for power savings in the Host CPU.
All four SUSPEND states are supported by LAN9500A/LAN9500Ai. SUSPEND3 is not
supported by LAN9500/LAN9500i.
(Note
2.1) Supports GPIO and “Good Packet” remote wakeup event. A “Good Packet”
(Note
DATASHEET
2.1) variations of USB suspend: SUSPEND0, SUSPEND1,
10
USB 2.0 to 10/100 Ethernet Controller
SMSC LAN950x Family
Datasheet