LAN91C96I-MS SMSC, LAN91C96I-MS Datasheet - Page 48

• Manufacturer Part Number: LAN91C96I-MS
• Description: Ethernet ICs Non-PCI 10 Mbps Ethernet MAC
• Manufacturer: SMSC
• Type: Single Chip MAC and PHYr

Specifications of LAN91C96I-MS

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 5 V
• Supply Voltage (min): 0 V
• Supply Current (max): 95 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 1.0 (10-24-08)
I/O SPACE - BANK0
For software compatibility with other LAN9000 parts all memory-related information is represented in 256 x
M byte units, where the multiplier M is determined by the MCR upper byte. M equals “1” for the
LAN91C96.
FREE MEMORY AVAILABLE - This register can be read at any time to determine the amount of free
memory. The register defaults to the MEMORY SIZE upon reset or upon the RESET MMU command.
MEMORY SIZE - This register can be read to determine the total memory size, and will always read 18H
(6144 bytes) for the LAN91C96.
I/O SPACE - BANK0
MEMORY RESERVED FOR TRANSMIT
Programming this value allows the host CPU to reserve memory to be used later for transmit, limiting the
amount of memory that receive packets can use up. When programmed for zero, the memory allocation
between transmit and receive is completely dynamic.
allocation is dynamic if the free memory exceeds the programmed value, while receive allocation requests
are denied if the free memory is less or equal to the programmed value. This register defaults to zero
upon reset. It is not affected by the RESET MMU command.
The value written to the MCR is a reserved memory space IN ADDITION TO ANY MEMORY
CURRENTLY IN USE. If the memory allocated for transmit plus the reserved space for transmit is required
to be constant (rather than grow with transmit allocations) the CPU should update the value of this register
after allocating or releasing memory.
The contents of MIR as well as the low byte of MCR are specified in 256* M bytes. The multiplier M is
determined by bits 11, 10 and 9 as follows:
OFFSET
OFFSET
0
0
0
0
A
8
LAN91C90
LAN91C90
LAN91C92/
LAN91C94
LAN91C95
LAN91C96
LAN91C100
MEMORY CONFIGURATION
0
0
0
0
MEMORY INFORMATION REGISTER
Memory Reserved for Transmit (in BYTES * 256 * M)
FREE MEMORY AVAILABLE (in BYTES* 256* M)
REGISTER
NAME
0
0
1
0
MEMORY SIZE (in BYTES* 256* M)
MEMORY SIZE REGISTER
DATASHEET
NAME
1
1
1
0
FFH
FFH
40H
12H
18H
18H
Page 48
LOWER BYTE READ/WRITE
Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
UPPER BYTE READ ONLY
0
0
1
1
Memory Size Multiplier “M”
When programmed for a non-zero value, the
M
TYPE
1
1
1
1
1
2
READ ONLY
0
0
0
0
TYPE
ACTUAL MEMORY
4608 bytes
6144 bytes
6144 bytes
128 kbytes
64 kbytes
16 kbytes
1
0
0
0
SYMBOL
SYMBOL
SMSC LAN91C96 5v&3v
MCR
MIR
1
0
0
0
Datasheet