DS26528G Maxim Integrated Products, DS26528G Datasheet - Page 223
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DS26528G
Manufacturer Part Number
DS26528G
Description
Network Controller & Processor ICs Octal E1-T1-J1 Singl e-Chip Transceiver (
Manufacturer
Maxim Integrated Products
Datasheet
1.DS26528G.pdf
(276 pages)
Specifications of DS26528G
Product
Framer
Number Of Transceivers
8
Supply Voltage (max)
3.465 V
Supply Voltage (min)
3.135 V
Supply Current (max)
875 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Package / Case
TE-CSBGA
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DS26528GA2
Manufacturer:
AFATECH
Quantity:
3 623
Part Number:
DS26528GA2
Manufacturer:
MAXIM/美信
Quantity:
20 000
Company:
Part Number:
DS26528GA5+
Manufacturer:
Maxim Integrated
Quantity:
10 000
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: All bits in this register are latched and can create interrupts.
Bit 7: Jitter Attenuator Limit Trip Clear (JALTC). This latched bit is set when a jitter attenuator limit trip condition
was detected and then removed.
Bit 6: Open-Circuit Clear (OCC). This latched bit is set when an open-circuit condition was detected at TTIP and
TRING and then removed.
Bit 5: Short-Circuit Clear (SCC). This latched bit is set when a short-circuit condition was detected at TTIP and
TRING and then removed.
Bit 4: Loss of Signal Clear (LOSC). This latched bit is set when a loss-of-signal condition was detected at RTIP
and RRING and then removed.
Bit 3: Jitter Attenuator Limit Trip Set (JALTS). This latched bit is set when the jitter attenuator limit trip condition
is detected.
Bit 2: Open-Circuit Detect (OCD). This latched bit is set when an open-circuit condition is detected at TTIP and
TRING. This bit is not functional in T1 CSU operating modes (T1 LBO 5, LBO 6, and LBO 7).
Bit 1: Short-Circuit Detect (SCD). This latched bit is set when a short-circuit condition is detected at TTIP and
TRING. This bit is not functional in T1 CSU operating modes (T1 LBO 5, LBO 6, and LBO 7).
Bit 0: Loss of Signal Detect (LOSD). This latched bit is set when an LOS condition is detected at RTIP and
RRING.
JALTC
7
0
LLSR
LIU Latched Status Register
1005h + (20h x n): where n = 0 to 7, for Ports 1 to 8
OCC
6
0
SCC
5
0
223 of 276
LOSC
4
0
JALTS
3
0
DS26528 Octal T1/E1/J1 Transceiver
OCD
2
0
SCD
1
0
LOSD
0
0
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