SI2401-FSR Silicon Laboratories Inc, SI2401-FSR Datasheet - Page 60

• Manufacturer Part Number: SI2401-FSR
• Description: Telecom Line Management ICs 2400b/s System Side 3rd Gen DAA Tech
• Manufacturer: Silicon Laboratories Inc
• Type: Integrated Global DAAr

Specifications of SI2401-FSR

• Product: Modem Module
• Supply Voltage (min): 3 V
• Supply Current: 15 mA
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 10 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Si2401
SED (RVC2). Ring Validation Control 2
Reset settings = 0001_1001 (0x19)
60
Bit
7:6
5:0
Name
Type
Bit
Reserved
RAS[5:0]
Name
D7
Read returns zero.
Ring Assertion Time.
These bits set the minimum ring frequency for a valid ring signal. During ring qualification,
a timer is loaded with the RAS[5:0] field upon a TIP/RING event and decrements at a reg-
ular rate. If a second or subsequent TIP/RING event occurs after the timer has timed out,
the frequency of the ring is too low, and the ring is invalidated. The difference between
RAS[5:0] and RMX[5:0] identifies the minimum duration between TIP/RING events to qual-
ify as a ring, in binary-coded increments of 2.0 ms (nominal). A TIP/RING event typically
occurs twice per ring tone period. At 20 Hz, TIP/RING events would occur every
1/(2 x 20 Hz) = 25 ms. To calculate the correct RAS[5:0] value for a frequency range
[f_min, f_max], the following equation should be used: RAS[5:0] = 1 / (2 x f_min).
D6
D5
Rev. 1.0
D4
Function
D3
RAS[5:0]
R/W
D2
D1
D0