CS8900A-IQR Cirrus Logic Inc, CS8900A-IQR Datasheet - Page 45
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CS8900A-IQR
Manufacturer Part Number
CS8900A-IQR
Description
Ethernet ICs IC 10Mbps Ethernet Controller 5V
Manufacturer
Cirrus Logic Inc
Datasheet
1.CS8900A-CQZ.pdf
(138 pages)
Specifications of CS8900A-IQR
Ethernet Connection Type
10Base- 2, 10Base- 5, 10Base- F, 10Base- T
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Product
Ethernet Controllers
Standard Supported
IEEE 802.3
Data Rate
10 Mbps
Maximum Operating Temperature
+ 85 C
Package / Case
LQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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DS271F5
ing bus signals are tied to the following pins:
See Section 3.2 on page 18.
After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state, which corre-
sponds to placing all the INTRQ pins in a high-impedance state. If an EEPROM is found, then the register's initial
value may be set by the EEPROM. See Section 3.3 on page 19.
Reset value is: XXXX XXXX XXXX X100
4.3.4 DMA Channel Number
(Read/Write, Address: PacketPage base + 0024h)
The DMA Channel register defines the DMA pins selected by the CS8900A. In the typical application, the following
bus signals are tied to the following pins:
See Section 3.2 on page 18 and Section 5.3 on page 90.
After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state which corre-
sponds to setting all DMRQ pins to high-impedance. If a EEPROM is found, then the register's initial value may be
set by the EEPROM. See Section 3.3 on page 19.
Reset value is: XXXX XXXX XXXX XX11
4.3.5 DMA Start of Frame
(Read only, Address: PacketPage base + 0026h)
The DMA Start of Frame Register contains a 16-bit value which defines the offset from the DMA base address to
the start of the most recently transferred received frame. See Section 5.3 on page 90.
CS8900A
Crystal LAN™ Ethernet Controller
Most significant byte of offset value
Address 0025h
Address 0027h
00h
CIRRUS LOGIC PRODUCT DATASHEET
Bus signal
Bus signal
DACK5
DACK6
DACK7
IRQ10
IRQ11
IRQ12
DRQ5
DRQ6
DRQ7
IRQ5
Typical pin connection
Typical pin connection
0000 0011b= All DMRQ pins high-impedance
DMACK0
DMACK1
DMACK2
INTRQ3
INTRQ0
INTRQ1
INTRQ2
DMRQ0
DMRQ1
DMRQ2
0000 0000b= pin DMRQ0 and DMACK0
0000 0001b= pin DMRQ1 and DMACK1
0000 0010b= pin DMRQ2 and DMACK2
Least significant byte of offset value
DMA channel assignment:
Address 0024h
Address 0026h
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