E-STE10/100A STMicroelectronics, E-STE10/100A Datasheet - Page 58

• Manufacturer Part Number: E-STE10/100A
• Description: Telecom ICs PCI Ethernet Contlr
• Manufacturer: STMicroelectronics

Specifications of E-STE10/100A

• Mounting Style: SMD/SMT
• Package / Case: PQFP-128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Registers and descriptors description
4.3
Note:
58/82
Transceiver(XCVR) registers
There are 11 16-bit registers supporting the transceiver portion of STE10/100A, including 7
basic registers defined according to clause 22 “Reconciliation Sublayer and Media
Independent Interface” and clause 28 “Physical Layer link signaling for 10 Mb/s and 100
Mb/s auto-negotiation on twisted pair” of the IEEE802.3u standard. In addition, 4 special
registers are provided for advanced chip control and status.
Since only double word access is supported for register R/W in the STE10/100A, the higher
word (bit 31~16) of the XCVR registers (XR0~XR10) should be ignored.
Table 9.
base address
Offset from
of CSR
b4h
b8h
d0h
d4h
d8h
bch
c0h
c4h
c8h
cch
dch
Transceiver registers list
Reg. index
XR10
XR0
XR1
XR2
XR3
XR4
XR5
XR6
XR7
XR8
XR9
100CTR
ANLPA
Name
XCIIS
PID1
PID2
XMC
XCR
XSR
ANA
ANE
XIE
XCVR control register
XCVR status register
PHY identifier 1
PHY identifier 2
Auto-negotiation advertisement register
Auto-negotiation link partner ability register
Auto-negotiation expansion register
XCVR mode control register
XCVR configuration information and interrupt status
register
XCVR interrupt enable register
100BASE-TX PHY control/status register
Register descriptions
STE10/100A