DS1847B-010 Maxim Integrated Products, DS1847B-010 Datasheet - Page 10
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DS1847B-010
Manufacturer Part Number
DS1847B-010
Description
Digital Potentiometer ICs
Manufacturer
Maxim Integrated Products
Datasheet
1.DS1847E-050.pdf
(17 pages)
Specifications of DS1847B-010
Number Of Pots
Dual
Taps Per Pot
256
Resistance
10 KOhms
Wiper Memory
Non Volatile
Digital Interface
Serial (2-Wire)
Operating Supply Voltage
3.3 V, 5 V
Supply Current
1 mA
Maximum Operating Temperature
+ 95 C
Minimum Operating Temperature
- 40 C
Supply Voltage (max)
5.5 V
Supply Voltage (min)
3 V
Package / Case
CSBGA-16
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DS1847B-010+
Manufacturer:
Maxim Integrated
Quantity:
10 000
Company:
Part Number:
DS1847B-010+T&R
Manufacturer:
Maxim Integrated
Quantity:
10 000
DS1847
2-WIRE SERIAL PORT OPERATION
The 2-wire serial port interface supports a bi-directional data transmission protocol with device
addressing. A device that sends data on the bus is defined as a transmitter, and a device receiving data as
a receiver. The device that controls the message is called a “master.” The devices that are controlled by
the master are “slaves.” The bus must be controlled by a master device that generates the serial clock
(SCL), controls the bus access, and generates the START and STOP conditions. The DS1847 operates as
a slave on the 2-wire bus. Connections to the bus are made via the open-drain I/O lines SDA and SCL.
The following I/O terminals control the 2-wire serial port: SDA, SCL, A0, A1, A2. Timing diagrams for
the 2-wire serial port can be found in Figures 3 and 4. Timing information for the 2-wire serial port is
provided in the AC Electrical Characteristics Table for 2-wire serial communications.
The following bus protocol has been defined:
§ Data transfer may be initiated only when the bus is not busy.
§ During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in
the data line while the clock line is HIGH will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change in the state of the data line from HIGH to LOW while the clock is HIGH
defines a START condition.
Stop data transfer: A change in the state of the data line from LOW to HIGH while the clock line is
HIGH defines the STOP condition.
Data valid: The state of the data line represents valid data when, after a START condition, the data line
is stable for the duration of the HIGH period of the clock signal. The data on the line can be changed
during the LOW period of the clock signal. There is one clock pulse per bit of data. Figures 3 and 4 detail
how data transfer is accomplished on the 2-wire bus. Depending upon the state of the R/W bit, two types
of data transfer are possible.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The
number of data bytes transferred between START and STOP conditions is not limited and is determined
by the master device. The information is transferred byte-wise and each receiver acknowledges with a
ninth bit.
Within the bus specifications a regular mode (100kHz clock rate) and a fast mode (400kHz clock rate) are
defined. The DS1847 works in both modes.
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the
reception of each byte. The master device must generate an extra clock pulse that is associated with this
acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a
way that the SDA line is a stable LOW during the HIGH period of the acknowledge-related clock pulse.
Of course, setup and hold times must be taken into account. A master must signal an end of data to the
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