TDA8754HL14BE-S NXP Semiconductors, TDA8754HL14BE-S Datasheet - Page 29
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TDA8754HL14BE-S
Manufacturer Part Number
TDA8754HL14BE-S
Description
Video ICs TRPL 8BIT VIDEO ADC
Manufacturer
NXP Semiconductors
Datasheet
1.TDA8754HL11C155.pdf
(57 pages)
Specifications of TDA8754HL14BE-S
Operating Supply Voltage
3 V to 3.6 V
Supply Current
180 mA
Maximum Operating Temperature
+ 70 C
Package / Case
SOT-486
Available Set Gain
6 dB
Bandwidth
700 MHz
Conversion Rate
140 msps
Maximum Power Dissipation
1.3 W
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Number Of Channels
3
Resolution
8 bit
Snr
48 dB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
TDA8754HL/14/C1,55
Philips Semiconductors
Table 32:
Table 33:
Table 34:
Table 35:
9397 750 14984
Product data sheet
PA4
0
0
:
1
1
VCO2
0
0
0
0
1
1
1
1
Bit
7
6
5 to 4
3 to 0
Bit
Symbol
Reset
Access
Symbol
CKEXT
SCH
CKREFO
EPSI[1:0]
DI[11:8]
Phase registers bits
VCO gain control
DIVMSB - PLL divider ratio (MSB) register (address 0Ch) bit allocation
DIVMSB - PLL divider ratio (MSB) register (address 0Ch) bit description
CKEXT
9.9 PLL divider registers
W
7
0
PA3
0
0
:
1
1
VCO1
0
0
1
1
0
0
1
1
Description
external clock selection
shift of pixel counter reference (Ckref) with one clock pixel period
enables the resynchronization edge of CKREFO to be selected; they are test bits
PLL divider ratio; these are the 4 MSBs of the 12-bit value; see
0 = internal PLL
1 = external clock
0 = not active
1 = active
00 = reset value for proper operation
SCH CKREFO
W
6
0
VCO0
0
1
0
1
0
1
0
1
PA2
0
0
:
1
1
EPSI1
W
5
0
Rev. 06 — 16 June 2005
VCO gain
(MHz/V)
13
30
60
60
105
105
135
no oscillation
PA1
0
0
:
1
1
EPSI0
W
4
0
DI11
W
3
0
Triple 8-bit video ADC up to 270 Msps
PA0
0
1
:
0
1
Table 38
DI10
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
W
2
1
Pixel clock frequency
(MHz)
12 to 22
22 to 45
45 to 62
62 to 85
85 to 120
120 to 176
176 to 270
-
Phase shift (deg)
0
11.25
:
337.50
348.75
DI9
TDA8754
W
1
1
DI8
W
29 of 57
0
0