STV9425 STMicroelectronics, STV9425 Datasheet - Page 12

• Manufacturer Part Number: STV9425
• Description: Video ICs On-Screen Disp Montr
• Manufacturer: STMicroelectronics
• Type: Multisync On-Screen Display For Monitorr

Specifications of STV9425

• Maximum Operating Temperature: + 70 C
• Package / Case: DIP-24
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

STV9425 - STV9425B - STV9426
FUNCTIONAL DESCRIPTION (continued)
VI - User Definable Character
The STV9425/25B/26 allows the user to dynami-
cally define character(s) for his own needs (for a
special LOGO for example). Like the ROM charac-
ters, a UDC is made of a 12 pixels x 18 slices dot
matrix, but one more slice is added for the vertical
shadowing when several UDCs are gathered to
make a special great character (see Figure 8).
In a UDC, each pixel is defined with a bit, 1 refers
to foreground, and 0 to background color. Each
slice of a UDC uses 2 bytes :
PX11is the left most pixel. Character slice address :
SLICEADDRESS = 38 x (CHARACTER NUMBER)
+ (SLICE NUMBER).
Where :
- CHARACTER NUMBER is the number given by
- SLICE NUMBER is the number given by the slice
VII - ROM Character Generator
The STV9425/25B/26 includes a ROM character
generator which is made of 128 alphanumeric or
graphic characters (see Table 1)
VIII - PLL
The PLL function of the STV9425/25B/26provides
the internal pixel clock locked on the horizontal
synchro signal and used by the display processor
to generate the R, G, B and fast blancking signals.
It is made of 2 PLLs. The first one analogic
(see Figure 9), provides a high frequency signal
locked on the crystal frequency. The frequency
multiplier is given by :
N = 2 (FM[3:0] + 3)
Where FM[3:0] is the value of the FREQUENCY
MULTIPLIER register.
Figure 9 : Analogic PLL
12/15
(even)
add +
the character code,
interpolator (n of the current slice of the strip :
1 < <18)
add
1
VCO
PX7 PX6 PX5 PX4 PX3 PX2 PX1 PX0
-
-
FILTRE
-
%N
N . F
-
XTAL
PX11 PX10 PX9 PX8
F
XTAL
The second PLL, full digital (see Figure 10), pro-
vides a pixel frequency locked on the horizontal
synchro signal. The ratio between the frequencies
of these 2 signals is :
M = 12 x (LD[5:0] + 1)
Where LD[5:0] is the value of the LINE DURATION
register.
Figure 10 : Digital PLL
VIII.1 - Programming of the PLL Registers
Frequency Multiplier (@3FF7)
This register gives the ratio between the crystal
frequency and the high frequency of the signal
used by the 2
clock. The value of this high frequency must be
near to 200MHz (for example if the crystal is a
8MHz, the value of FM must be equal to 10) and
greater than 6 x (pixel frequency).
Initial Pixel Period (@3FF6)
This register allows to increase the speed of the
convergence of the PLL when the horizontal fre-
quency changes (new graphic standart). The rela-
tionshipbetween FM[3:0], PP[7:0],LD[5:0],F
and F
Locking Condition Time Constant (@ 3FF4)
This register gives the constants AS[2:0] and
BS[2:0] used by the algo partof the PLL(see Figure
10) to calculate, from the phase error, err(n), the
new value, D(n), of the division of the high fre-
quency signal to provide the pixel clock. These two
constants are used only in locking condition, which
is true, if the phase error is less than a fixed value
during at least, 4 scan lines. If the phase error
becomes greater than the fixed value, the PLL is
not in locking condition but in capture process. In
this case, the algo part of the PLL used the other
constants, AF[2:0] and BF[2:0], given by the next
register.
Capture Process Time Constant (@ 3FF5)
The choice between these two time constants
(locking condition or capture process) allows to
decreasethe capture processtime by changingthe
time response of the PLL.
N . F
PP[7:0]
XTAL
XTAL
is :
round
D(n)
nd
%D
PLL to provide, by division, the pixel
8
12
2
FM[3:0]
LD[5:0]
ALGO
%M
M . F
H-SYNC
1
3
F
F
HSYNC
XTAL
err(n)
F
H-SYNC
HSYNC
24