HUF75645P3 Fairchild Semiconductor, HUF75645P3 Datasheet - Page 8

• Manufacturer Part Number: HUF75645P3
• Description: MOSFET N-CH 100V 75A TO-220AB
• Manufacturer: Fairchild Semiconductor
• Series: UltraFET™r

Specifications of HUF75645P3

• Fet Type: MOSFET N-Channel, Metal Oxide
• Fet Feature: Logic Level Gate
• Rds On (max) @ Id, Vgs: 14 mOhm @ 75A, 10V
• Drain To Source Voltage (vdss): 100V
• Current - Continuous Drain (id) @ 25° C: 75A
• Vgs(th) (max) @ Id: 4V @ 250µA
• Gate Charge (qg) @ Vgs: 238nC @ 20V
• Input Capacitance (ciss) @ Vds: 3790pF @ 25V
• Power - Max: 310W
• Mounting Type: Through Hole
• Package / Case: TO-220-3 (Straight Leads)
• Configuration: Single
• Transistor Polarity: N-Channel
• Resistance Drain-source Rds (on): 0.014 Ohm @ 10 V
• Drain-source Breakdown Voltage: 100 V
• Gate-source Breakdown Voltage: +/- 20 V
• Continuous Drain Current: 75 A
• Power Dissipation: 310000 mW
• Maximum Operating Temperature: + 175 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 55 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SABER Electrical Model
REV 21 May 1999
template ta75645 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is = 3.00e-12, cjo = 5.32e-9, tt = 7.4e-8, xti = 5, m = 0.68)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 5.55e-9, is = 1e-30, vj=1.0, m = 0.8)
m..model mmedmod = (type=_n, vto = 3.13, kp = 10, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 3.51, kp = 93, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 2.65, kp = 0.11, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -6.2, voff = -2.4)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -2.4, voff = -6.2)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1.8, voff = 0.5)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -1.8)
c.ca n12 n8 = 5.31e-9
c.cb n15 n14 = 5.31e-9
c.cin n6 n8 = 3.56e-9
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
i.it n8 n17 = 1
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 5.1e-9
l.lsource n3 n7 = 4.4e-9
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1 = 9.9e-4, tc2 = -1.3e-6
res.rdbody n71 n5 = 1.78e-3, tc1 = 2.25e-3, tc2 = 1.e-5
res.rdbreak n72 n5 = 2.15e-1, tc1 = 8e-4, tc2 = 3e-6
res.rdrain n50 n16 = 7.8e-3, tc1 = 9.4e-3, tc2 = 2.93e-5
res.rgate n9 n20 = 0.83
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 26
res.rlsource n3 n7 = 11
res.rslc1 n5 n51 = 1e-6, tc1 = 2.63e-3, tc2 = 1.05e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 1.65e-3, tc1 = 1e-3, tc2 = 1e-6
res.rvtemp n18 n19 = 1, tc1 = -2.87e-3, tc2 = -2.21e-6
res.rvthres n22 n8 = 1, tc1 = -2.57e-3, tc2 = -7.05e-6
spe.ebreak n11 n7 n17 n18 = 115.5
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/205))** 3.5))
}
}
©2001 Fairchild Semiconductor Corporation
GATE
1
RLGATE
LGATE
9
RGATE
CA
12
20
EVTEMP
+
S1A
S1B
ESG
18
22
EGS
13
8
+
-
-
13
6
8
10
+
+
-
-
14
13
6
8
6
RSLC2
S2A
S2B
DPLCAP
EVTHRES
+
EDS
19
8
15
CB
CIN
-
+
-
5
8
5
MSTRO
14
51
21
RDRAIN
RSLC1
50
ISCL
16
8
MMED
8
RDBREAK
DBREAK
IT
RSOURCE
MWEAK
17
EBREAK
RVTHRES
RBREAK
72
11
+
-
17
18
HUF75645P3, HUF75645S3S Rev. B
7
+
-
18
22
RVTEMP
19
71
RLSOURCE
RLDRAIN
LSOURCE
VBAT
RDBODY
DBODY
LDRAIN
SOURCE
DRAIN
2
3