MT88E46AS1 Zarlink, MT88E46AS1 Datasheet - Page 19

• Manufacturer Part Number: MT88E46AS1
• Description: Caller ID CMOS 3.58MHz 3.3V/5V 20-Pin SOIC Tube
• Manufacturer: Zarlink

Specifications of MT88E46AS1

• Package: 20SOIC
• Telecommunication Standards Supported: Bellcore GR-30-CORE|SR-TSV-002476|TIA/EIA-716|TIA/EIA-777
• Fabrication Technology: CMOS
• Maximum Data Rate: 1.212 KBd
• Typical Operating Supply Voltage: 3.3|5 V
• Typical Supply Current: 4.3 mA
• Minimum Operating Temperature: -40 °C
• Maximum Operating Temperature: 85 °C
• Operating Frequency: 3.58 MHz

Data Sheet
CAS
DET
(Output)
TIP/RING
DATA
(Output)
DCLK
(Output)
DR
(Output)
Note: The relationship between DATA bit boundary and DCLK is symbolic only. In reality, the DATA bit boundary will jitter with respect to the
DCLK falling edges.
Demodulated Data
(Internal Signal)
DR (Data Ready)
(Output)
DCLK (Data Clock)
(Schmitt Input)
DATA
(Output)
The DCLK input must be low before and after DR falling edge.
Note 1: DCLK occurs during DR low and returns DR to high.
Note 2: DCLK occurs after DR, so DR is low for half a nominal bit time.
Note 3: When framing error (trailing stop bit a 0 instead of a 1) is not checked, the microcontroller only needs to send 8 DCLK pulses to
shift the byte out.
b7
stop
b6
b7
start
stop
t
Word N
CH
Word N-1
b0 b1 b2 b3 b4 b5 b6 b7
start
>t
7
7
DDS
b0 b1 b2 b3 b4 b5 b6 b7
Figure 14 - FSK Data Interface Timing - Mode 0
Figure 15 - FSK Data Interface Timing - Mode 1
t
IDD
stop
stop
>t
Note 1
0
DDH
Figure 13 - CAS Detection Timing
start
1
2
Word N
t
DET1
t
CL
0
3
1/f
4
stop
DCLK1
1
5
start
stop
6
b0 b1 b2 b3 b4 b5 b6 b7
start
t
DET2
2
7
t
CRD
Word N+1
t
RL
b0 b1 b2 b3 b4 b5 b6 b7
Note 3
3
t
DW
4
= 416µs nominal
stop
5
See ‘AC Electrical Characteristics -
CAS Detection’ for t
values.
stop
1/f
6
start
DCLK0
stop
b0 b1 b2 b3 b4 b5
start
7
Note 2
b0 b1 b2 b3
t
DET1
RL
MT88E46
stop
and t
DET2
0
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