SI3200-G-GS Silicon Laboratories Inc, SI3200-G-GS Datasheet - Page 78

• Manufacturer Part Number: SI3200-G-GS
• Description: SLIC 2-CH 63dB 45mA 3.3V 6-Pin SMD
• Manufacturer: Silicon Laboratories Inc
• Series: ProSLIC®r

Specifications of SI3200-G-GS

• Package: 6SMD
• Number Of Channels Per Chip: 2
• Polarity Reversal: Yes
• Longitudinal Balanced: 63 dB
• Loop Current: 45 mA
• Minimum Operating Supply Voltage: 3.13 V
• Typical Operating Supply Voltage: 3.3 V
• Typical Supply Current: 0.11 mA
• Function: Subscriber Line Interface Concept (SLIC), CODEC
• Interface: GCI, PCM, SPI
• Number Of Circuits: 2
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 110µA
• Power (watts): 941mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Includes: Battery Switching, BORSCHT Functions, DTMF Generation and Decoding, FSK Tone Generation, Modem and Fax Tone Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Si3232
MSTRSTAT: Master Initialization Status (Register Address 3)
(Register type: Initialization/single value instance for both channels)
Reset settings = 0x00
78
Name PLLFAULT FSFAULT PCFAULT
Type
Bit
Bit
7
6
5
4
3
2
1
0
PLLFAULT
PCFAULT
FSFAULT
SRCLR
PLOCK
FSDET
PCVAL
FSVAL
Name
R/W
D7
PLL Lock Fault Status.
This bit is set when the PLOCK bit transitions low, indicating loss of PLL lock. Writing 1 to
this bit clears the status.
0 = PLL lock is valid.
1 = PLL has lost lock.
FSYNC Clock Fault Status.
This bit is set when the FSVAL and FSDET bits transition low, indicating loss of valid
FSYNC signal or invalid FSYNC-to-PCLK ratio. Writing 1 to this bit clears the status.
0 = Correct FSYNC to PCLK ration present.
1 = FSYNC to PCLK ratio lost.
PCM Clock Fault Status.
This bit will be set when the PCVAL bit transitions low. Writing 1 to this bit clears the status.
0 = Valid PCLK signal present.
1 = No valid PCLK signal present.
SRAM Clear Status Detect.
0 = SRAM clear operation not initiated or in progress.
1 = SRAM clear operation has completed.
PLL Lock Detect.
Indicates the internal PLL is locked relative to FSYNC.
0 = PLL has lost lock relative to FSYNC.
1 = PLL locked relative to FSYNC.
FSYNC to PCLK Ratio Detect.
Indicates a valid FSYNC to PCLK ratio has been detected.
0 = Invalid FSYNC to PCLK ratio detected.
1 = Correct FSYNC to PCLK ratio present.
FSYNC Clock Valid.
Indicates that a minimum valid FSYNC signal is present.
0 = FSYNC signal is not valid.
1 = FSYNC signal is present.
PCM Clock Valid.
Indicates that a minimum valid PCLK signal is present.
0 = PCLK signal is ≤ 128 kHz.
1 = PCLK signal is ≥ 128 kHz.
R/W
D6
R/W
D5
SRCLR
Preliminary Rev. 0.96
D4
R
PLOCK
D3
R
Function
FSDET
D2
R
FSVAL
D1
R
PCVAL
D0
R