LE58QL061BVC Zarlink, LE58QL061BVC Datasheet - Page 27

• Manufacturer Part Number: LE58QL061BVC
• Description: QUAD, SLAC, PROG CODEC, 3.3V, GCI, 20 I/0, PQT44, LEAD FREE
• Manufacturer: Zarlink

GCI Timing Specifications
Notes:
1.
2.
Symbol
t
wH
If DCL has jitter, care must be taken to ensure that all setup, hold, and pulse width requirements are met.
The Data Clock (DCL) can be stopped in the high or low state without loss of information.
J
t
t
t
t
t
t
DCL
wFH
dDC
t
dDF
t
t
DCL
t
r
r
hD
sF
hF
sD
, t
, t
, t
f
f
wL
Signal
DCL
DCL
DCL
DCL
V
DU
DU
DD
DD
FS
FS
FS
FS
IL
Rise/fall time
DCL jitter
Period
Pulse width
Rise/fall time
Setup time
Hold time
High pulse width
Delay from DCL edge
Delay from FS edge
Data setup
Data hold
V
IH
Parameter
Figure 16. Master Clock Timing
F
F
F
F
DCL
DCL
DCL
DCL
40
= 2.048 kHz
= 4.096 kHz
= 2.048 kHz
= 4.096 kHz
Zarlink Semiconductor Inc.
27
39
twH + 20
37
Min
130
90
70
50
50
41
Typ
488
244
38
t
DCL
Max
100
150
60
50
50
60
– 50
Unit
ns
Notes
1
2