LAN9311-NZW Standard Microsystem (Smsc), LAN9311-NZW Datasheet - Page 230

• Manufacturer Part Number: LAN9311-NZW
• Description: Ethernet Switch 2-Port 10Mbps/100Mbps 128-Pin XVTQFP
• Manufacturer: Standard Microsystem (Smsc)

Specifications of LAN9311-NZW

• Package: 128XVTQFP
• Phy/transceiver Interface: MII
• Number Of Primary Switch Ports: 2
• Maximum Data Rate: 100 Mbps
• Internal Memory Buffer Size: 32 KB
• Vlan Support: Yes
• Power Supply Type: Analog
• Minimum Single Supply Voltage: 3 V
• Maximum Single Supply Voltage: 3.6 V
• Maximum Supply Current: 0.295 A
• Maximum Power Dissipation: 1070 mW

Revision 1.7 (06-29-10)
14.2.6
14.2.6.1
BITS
31:7
6
5
4
3
2
RESERVED
Port 1 Backpressure Enable (BP_EN_1)
This bit enables/disables the generation of half-duplex backpressure on
switch Port 1.
0: Disable backpressure
1: Enable backpressure
Port 1 Current Duplex (CUR_DUP_1)
This bit indicates the actual duplex setting of switch Port 1.
0: Full-Duplex
1: Half-Duplex
Port 1 Current Receive Flow Control Enable (CUR_RX_FC_1)
This bit indicates the actual receive flow setting of switch Port 1.
0: Flow control receive is currently disabled
1: Flow control receive is currently enabled
Port 1 Current Transmit Flow Control Enable (CUR_TX_FC_1)
This bit indicates the actual transmit flow setting of switch Port 1.
0: Flow control transmit is currently disabled
1: Flow control transmit is currently enabled
Port 1 Full-Duplex Receive Flow Control Enable (RX_FC_1)
When the MANUAL_FC_1 bit is set, or Auto-Negotiation is disabled, this bit
enables/disables the detection of full-duplex Pause packets on switch Port 1.
0: Disable flow control receive
1: Enable flow control receive
Switch Fabric
This section details the memory mapped System CSR’s which are related to the Switch Fabric. The
flow control of all three ports of the switch fabric can be configured via the memory mapped System
CSR’s MANUAL_FC_1, MANUAL_FC_2 and MANUAL_FC_MII. The MAC address used by the switch
for Pause frames is configured via the SWITCH_MAC_ADDRH and SWITCH_MAC_ADDRL registers.
In addition, the SWITCH_CSR_CMD, SWITCH_CSR_DATA and SWITCH_CSR_DIRECT_DATA
registers serve as a memory mapped accessible interface to the full range of otherwise inaccessible
switch control and status registers. A list of all the switch fabric CSRs can be seen in
additional information on the switch fabric, including a full explanation on how to use the switch fabric
CSR interface registers, refer to
the Switch Fabric CSR’s that are accessible via these interface registers, refer to section
"Switch Fabric Control and Status
Port 1 Manual Flow Control Register (MANUAL_FC_1)
This read/write register allows for the manual configuration of the switch Port 1 flow control. This
register also provides read back of the currently enabled flow control settings, whether set manually
or Auto-Negotiated. Refer to
information.
Note: The flow control values in the PHY_AN_ADV_1 register (see
within the PHY are not affected by the values of this register.
Offset:
1A0h
DESCRIPTION
Section 6.2.3, "Flow Control Enable Logic," on page 58
Chapter 6, "Switch Fabric," on page
Registers".
DATASHEET
230
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Size:
32 bits
55. For detailed descriptions of
Section 14.4.2.5, on page
TYPE
R/W
R/W
SMSC LAN9311/LAN9311i
RO
RO
RO
RO
Table
for additional
Section 14.5,
DEFAULT
Note 14.4
Note 14.5
Note 14.5
Note 14.5
Note 14.6
14.12. For
Datasheet
-
295)