AD7945BR Analog Devices Inc, AD7945BR Datasheet - Page 6

• Manufacturer Part Number: AD7945BR
• Description: DAC 1-CH R-2R 12-Bit 20-Pin SOIC W
• Manufacturer: Analog Devices Inc

Specifications of AD7945BR

• Package: 20SOIC W
• Resolution: 12 Bit
• Conversion Rate: 1.7 MSPS
• Architecture: R-2R
• Digital Interface Type: Parallel
• Number Of Outputs Per Chip: 1
• Output Type: Current
• Full Scale Error: ±2 LSB
• Integral Nonlinearity Error: ±0.5 LSB
• Maximum Settling Time: 0.6(Typ) us
• Rohs Status: RoHS non-compliant
• Settling Time: 600ns
• Number Of Bits: 12
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 25µW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Number Of Channels: 1
• Interface Type: Parallel
• Single Supply Voltage (typ): 5V
• Dual Supply Voltage (typ): Not RequiredV
• Power Supply Requirement: Single
• Single Supply Voltage (min): 4.5V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Package Type: SOIC W
• Lead Free Status / Rohs Status: Not Compliant

AD7943/AD7945/AD7948
AD7945 TIMING SPECIFICATIONS
Parameter
t
t
t
t
t
NOTES
1
Specifications subject to change without notice.
AD7948 TIMING SPECIFICATIONS
Parameter
t
t
t
t
t
t
t
NOTES
1
Specifications subject to change without notice.
All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
DS
DH
CS
CH
WR
All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
DS
DH
CWS
CWH
LWS
LWH
WR
Limit @
V
35
10
60
0
60
Limit @
45
10
0
0
0
0
60
V
DD
DD
= +3 V to +3.6 V
= +3 V to +3.6 V
DB7–DB0
DB11–DB0
CSMSB
CSLSB
LDAC
WR
WR
CS
t
CWS
Limit @
V
20
10
40
0
40
Limit @
V
30
10
0
0
0
0
40
Figure 3. AD7945 Timing Diagram
Figure 4. AD7948 Timing Diagram
t
DD
DD
DS
1
1
= +4.5 V to +5.5 V
(T
= +4.5 V to +5.5 V
t
(T
WR
A
VALID
DATA
A
= T
= T
MIN
MIN
to T
t
t
to T
CWH
DH
t
–6–
MAX
CS
MAX
t
, unless otherwise noted)
WR
, unless otherwise noted)
t
t
CWS
LWS
t
DATA VALID
DS
t
DS
Units
ns min
ns min
ns min
ns min
ns min
Units
ns min
ns min
ns min
ns min
ns min
ns min
ns min
t
WR
t
t
VALID
DATA
DH
CH
t
t
CWH
LWH
t
DH
Description
Data Setup Time
Data Hold Time
Chip Select Setup Time
Chip Select Hold Time
Write Pulsewidth
Description
Data Setup Time
Data Hold Time
CSMSB or CSLSB to WR Setup Time
CSMSB or CSLSB to WR Hold Time
LDAC to WR Setup Time
LDAC to WR Hold Time
Write Pulsewidth
REV. B