TSI107D-100JEY Integrated Device Technology (Idt), TSI107D-100JEY Datasheet
![no-image](/images/manufacturer_photos/0/3/333/integrated_device_technology__idt__sml.jpg)
TSI107D-100JEY
Manufacturer Part Number
TSI107D-100JEY
Description
Host Bridge 503-Pin FCBGA
Manufacturer
Integrated Device Technology (Idt)
Datasheet
1.TSI107D-100JEY.pdf
(2 pages)
Specifications of TSI107D-100JEY
Package
503FCBGA
Operating Temperature
0 to 105 °C
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TSI107D-100JEY
Manufacturer:
ADI
Quantity:
609
Company:
Part Number:
TSI107D-100JEY
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Device Overview
The IDT Tsi107 Host Bridge for PowerPC provides system interconnect
between PowerPC processors, PCI peripherals, and local memory. PCI
support allows system designers to design systems quickly using
peripherals already developed for PCI and the other standard interfaces
available in the personal computer hardware environment.
The Tsi107 provides many of the other necessities for embedded appli-
cations, including a high-performance memory controller and dual-
processor support; two-channel flexible DMA controller; an interrupt
controller; an I2O-ready message unit; an inter-integrated circuit
controller (I2C); and low-skew clock drivers. The Tsi107 contains an
Embedded Programmable Interrupt Controller (EPIC) featuring five
hardware interrupts (IRQs), as well as 16 serial interrupts and four
timers. The Tsi107 uses an advanced, 2.5V CMOS process technology,
and is fully compatible with TTL devices.
Block Diagram
IEEE1149.1
Multiprocessor and Local Bus Slave Support
The Tsi107 supports a programmable interface to microprocessors
implementing the PowerPC architecture, operating at bus frequencies
up to 133 MHz. The Tsi107 processor interface allows for a variety of
system configurations by providing support for a second processor and
a local bus slave.
2009 Integrated Device Technology, Inc.
Five IRQs/
Interrupts
16 Serial
Boundry
Master/
Slave
Scan
Controller
Message
Interrupt
Timers
DMA
(I 2 O)
JTAG
Unit
EPIC
I 2 C
32-bit, up to 66 MHz
PCI Bus (Rev. 2.1)
Logic Block
Peripheral
32/64-bit Data and 32-bit Address
PCI Interface
Processor Interface
Control Unit
66-133 MHz
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
Central
®
Five Request/
Grant Pairs
Arbiter
Data Path
Memory
Fan Out
Buffers
80C2000_BK001_02
Tsi107
Product Brief
DLL
PLL
PCI Bus
Clocks
Data Bus
(32/64-bit)
with 8-bit
Parity or
ECC
Memory/
ROM/
Port X
Control/
Address
SDRAM
and CPU
Clocks
1 of 2
™
Integrated Memory Controller
The memory interface controls processor and PCI interactions to main
memory. It supports a variety of programmable DRAM (FPM, EDO),
SDRAM, and ROM/Flash ROM configurations. These support timing at
speeds of up to 133 MHz.
PCI Bus Support
The Tsi107 PCI interface is designed to connect the processor and
memory buses to the PCI local bus without the need for “glue” logic. It
runs at speeds up to 66 MHz. The Tsi107 acts as either a master or
target on the PCI bus and contains a PCI bus arbitration unit which
reduces the need for an equivalent external unit. This reduces the total
system complexity and cost.
Features
Processor Interface
Memory Interface
PCI Interface
Host Bridge for PowerPC
• Supports the Motorola MPC603e, MPC7xx, and MPC74xx
• Supports the IBM PowerPC 603e, and PowerPC 7xx processors
• Processor bus frequency up to 133 MHz
• 64/32-bit data bus, 32-bit address bus
• I/O voltage: 2.5V or 3.3V
• SMP support for a second processor
• Full memory coherency, integrated arbiter and slave peripheral
• High-bandwidth (32-bit/64-bit) data bus up to 133 MHz
• Programmable timing: supports either DRAM (FPM, EDO) or
• Supports one to eight banks: 4, 16, 64, 128, and/or 256-bit
• 1 GB RAM space, 144 MB ROM space
• 8, 32, or 64-bit ROM/Flash ROM
• 8, 32, or 64-bit general-purpose I/O port: uses ROM controller
• Supports parity, read-modify-write, or error-correcting code (ECC)
• Compliant with PCI specification, (revision 2.1)
• 32-bit PCI interface — up to 66 MHz
• 5.0 V compatible
• Read and write buffers to improve PCI performance
• Selectable big or little-endian operation
• PCI interface acts as host or agent — allows multiple Tsi107s on
processors
support
SDRAM
DRAMs/SDRAMs
interface with address strobe
one PCI bus
October 26, 2009
®
Related parts for TSI107D-100JEY
TSI107D-100JEY Summary of contents
Page 1
Device Overview The IDT Tsi107 Host Bridge for PowerPC provides system interconnect between PowerPC processors, PCI peripherals, and local memory. PCI support allows system designers to design systems quickly using peripherals already developed for PCI and the other standard ...
Page 2
Tsi107 Product Brief • Arbiter supports up to five other PCI devices • Two-channel integrated DMA controller • Intelligent Input/Output (I2O) message controller • Doorbell and messaging registers • Inter-Integrated Circuit (I2C) Controller • Embedded Programmable Interrupt Controller (EPIC) • ...