874005AG-04LF Integrated Device Technology (Idt), 874005AG-04LF Datasheet - Page 7

• Manufacturer Part Number: 874005AG-04LF
• Description: PCI Express Jitter Attenuator 24-Pin TSSOP Tube
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 874005AG-04LF

• Package: 24TSSOP
• Operating Temperature: 0 to 70 °C

P
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. To achieve optimum jitter
perfor mance, pow er supply isolation is required. The
ICS874005-04 provides separate power supplies to isolate
any high switching noise from the outputs to the internal PLL.
V
power supply plane through vias, and 0.01µF bypass
capacitors should be used for each pin. Figure 1 illustrates
this for a generic V
that an additional10
capacitor be connected to the V
R
I
LVCMOS C
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
W
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
IDT
NPUTS
DD
OWER
ECOMMENDATIONS FOR
ICS874005-04
PCI EXPRESS™ JITTER ATTENUATOR
IRING THE
™
, V
/ ICS
DDA
:
™
S
and V
PCI EXPRESS™ JITTER ATTENUATOR
UPPLY
ONTROL
D
IFFERENTIAL
DDO
resistor can be used.
P
F
INS
ILTERING
DD
should be individually connected to the
pin and also shows that V
resistor along with a 10µF bypass
U
NUSED
I
NPUT TO
T
ECHNIQUES
DDA
F
pin.
IGURE
I
NPUT AND
Single Ended Clock Input
A
CCEPT
2. S
A
PPLICATION
INGLE
O
S
DDA
UTPUT
INGLE
E
C1
0.1u
requires
NDED
V_REF
DD
/2 is
E
P
NDED
S
INS
IGNAL
7
I
L
NFORMATION
O
LVDS O
All unused LVDS output pairs can be either left floating or
ter minated with 100
recommend that there is no trace attached.
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
and R2/R1 = 0.609.
D
1K
EVELS
R1
1K
R2
UTPUTS
RIVING
VDD
UTPUTS
CLK
nCLK
D
:
IFFERENTIAL
F
IGURE
1. P
V
V
I
DDA
NPUT
DD
across. If they are left floating, we
OWER
ICS874005AG-04 REV. A JULY 29, 2008
DD
.01 F
S
.01 F
= 3.3V, V_REF should be 1.25V
UPPLY
3.3V
F
10
ILTERING
10 F