89HPES24T6G2ZCAL Integrated Device Technology (Idt), 89HPES24T6G2ZCAL Datasheet - Page 13

• Manufacturer Part Number: 89HPES24T6G2ZCAL
• Description: PCI System Interconnect Switch 324-Pin FCBGA Tray
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 89HPES24T6G2ZCAL

• Package: 324FCBGA
• Operating Temperature: 0 to 70 °C

IDT 89HPES24T6G2 Data Sheet
T
DATA
T
T
T
T
PCIe Receive
UI
T
T
MAX JITTER
T
T
T
T
T
TX-IDLE-TO-DIFF-
TX-SKEW
MIN-PULSED
TX-HF-DJ-DD
RF-MISMATCH
RX-EYE (with jitter)
RX-EYE-MEDIUM TO
RX-SKEW
RX-HF-RMS
RX-HF-DJ-DD
RX-LF-RMS
RX-MIN-PULSE
1.
Parameter
Minimum, Typical, and Maximum values meet the requirements under PCI Specification 2.0
Maximum time to transition from valid idle to diff data
Transmitter data skew between any 2 lanes
Minimum Instantaneous Lone Pulse Width
Transmitter Deterministic Jitter > 1.5MHz Bandwidth
Rise/Fall Time Differential Mismatch
Unit Interval
Minimum Receiver Eye Width (jitter tolerance)
Max time between jitter median & max deviation
Lane to lane input skew
1.5 — 100 MHz RMS jitter (common clock)
Maximum tolerable DJ by the receiver (common clock)
10 KHz to 1.5 MHz RMS jitter (common clock)
Minimum receiver instantaneous eye width
GPIO
GPIO[10:0]
1.
they are asynchronous. Note that GPIO{6:3} pins are not available in the 19mm package.
2.
GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if
The values for this symbol were determined by calculation, not by testing.
Signal
1
Description
Table 10 PCIe AC Timing Characteristics (Part 2 of 2)
Symbol
Tpw
Table 11 GPIO AC Timing Characteristics
2
Referenc
e Edge
None
13 of 51
Min
399.88
0.4
Min Max Unit
50
1
Gen 1
Typ
400
NA
NA
NA
NA
NA
NA
NA
—
1
ns
Max
400.12
1.3
0.3
20
8
1
Reference
Diagram
Timing
Min
199.94
0.9
0.4
0.6
1
Gen 2
Typ
1
Max
September 13, 2010
200.06
0.15
1.3
0.1
3.4
4.2
88
8
8
1
Units
ns
ns
ps
ns
ps
ps
ps
UI
UI
UI
UI
UI
UI