74FST6800QG Integrated Device Technology (Idt), 74FST6800QG Datasheet - Page 4

• Manufacturer Part Number: 74FST6800QG
• Description: Bus Switch 1-Element 10-IN 24-Pin QSOP Tube
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 74FST6800QG

• Package: 24QSOP
• Configuration: 10 x 1:1
• Logic Family: FST
• Logic Function: Bus Switch
• Number Of Elements Per Chip: 1
• Number Of Outputs Per Chip: 10
• Typical Operating Supply Voltage: 5 V
• Maximum On Resistance: 15 Ohm
• Maximum High Level Output Current: -128 mA
• Maximum Low Level Output Current: 128 mA
• Maximum Operating Supply Voltage: 5.25 V
• Minimum Operating Supply Voltage: 4.75 V
• Maximum Propagation Delay Time @ Maximum Cl: 0.25@5V ns

TEST CIRCUITS AND WAVEFORMS
ASYNCHRONOUS CONTROL
SYNCHRONOUS CONTROL
IDT74FST6800
10-BIT BUS SWITCH WITH PRECHARGED OUTPUTS
Generator
CLOCK ENABLE
INPUT TRANSITION
INPUT TRANSITION
Pulse
OPPOSITE PHASE
SAME PHASE
PRESET
PRESET
TIMING
CLEAR
CLEAR
INPUT
INPUT
DATA
OUTPUT
V
ETC.
ETC.
Set-up, Hold, and Release Times
IN
Test Circuits for All Outputs
R
Propagation Delay
T
D.U.T
.
V
t
PLH
t
CC
PLH
t
t
SU
SU
V
OUT
t
REM
t
H
t
t
C
PHL
PHL
50pF
L
t
H
Octal Link
500Ω
500Ω
Octal Link
Octal Link
3V
1.5V
0V
V
1.5V
V
3V
1.5V
0V
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
OH
OL
4
DEFINITIONS:
C
R
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; t
SWITCH POSITION
L
T
= Load capacitance: includes jig and probe capacitance.
= Termination resistance: should be equal to Z
NORMALLY
NORMALLY
CONTROL
HIGH-LOW-HIGH
LOW-HIGH-LOW
OUTPUT
OUTPUT
INPUT
All Other Tests
HIGH
LOW
Disable Low
Enable Low
Open Drain
Test
PULSE
PULSE
SWITCH
CLOSED
SWITCH
OPEN
ENABLE
Enable and Disable Times
t
t
PZH
PZL
Pulse Width
INDUSTRIAL TEMPERATURE RANGE
1.5V
1.5V
3.5V
0V
t
PHZ
OUT
t
F
W
DISABLE
≤ 2.5ns; t
of the Pulse Generator.
t
PLZ
Switch
Closed
Open
R
0.3V
0.3V
≤ 2.5ns.
Octal Link
Octal Link
3V
1.5V
0V
3.5V
V
V
0V
OL
OH
1.5V
1.5V