49FCT3805QG Integrated Device Technology (Idt), 49FCT3805QG Datasheet - Page 6

• Manufacturer Part Number: 49FCT3805QG
• Description: Clock Buffer 10-OUT 20-Pin QSOP Tube
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 49FCT3805QG

• Package: 20QSOP
• Number Of Outputs Per Chip: 10
• Maximum Propagation Delay Time @ Maximum Cl: 5.8@3.3V ns
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

TEST CIRCUITS AND WAVEFORMS
OUTPUT
IDT49FCT3805/A
3.3V CMOS BUFFER/CLOCK DRIVER
OUTPUT
NORMALLY
NORMALLY
CONTROL
Generator
INPUT
OUTPUT
OUTPUT
INPUT
Pulse
INPUT
HIGH
LOW
SWITCH
CLOSED
SWITCH
OPEN
ENABLE
V
IN
t
t
Test Circuits for All Outputs
PZL
PZH
t
PLH
t
Output Skew - t
Pulse Skew - t
PLH
t
R
SK(p)
Package Delay
T
t
R
1.5V
1.5V
3.5V
0V
D.U.T.
V
= |t
CC
PHL -
t
PHZ
DISABLE
t
V
SK(P)
PLH
OUT
SK(X)
t
PHL
t
t
PHL
PLZ
|
t
F
0.3V
0.3V
50pF
0.8V
2.0V
V
1.5V
3V
1.5V
0V
V
3V
1.5V
0V
3.5V
V
0V
V
OH
OL
OH
OL
3V
1.5V
0V
500
500
V
1.5V
V
OL
OH
GND
6V
6
SWITCH POSITION
DEFINITIONS:
C
R
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH
2. Pulse Generator for All Pulses: f ≤ 1.0MHz; t
L
T
= Load capacitance: includes jig and probe capacitance.
= Termination resistance: should be equal to Z
OUTPUT 1
OUTPUT 2
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
INPUT
PACKAGE 1
PACKAGE 2
Disable HIGH
Enable HIGH
Disable LOW
Enable LOW
OUTPUT
OUTPUT
INPUT
Test
t
SK(o)
t
SK(t)
= |t
Package Skew - t
Output Skew - t
= |t
t
PLH2 -
PLH1
t
PLH2
PLH2 -
t
SK(o)
t
t
PLH1
PLH1
t
t
PLH2
PLH1
t
|
SK(t)
or
F
t
|
|t
PHL1
OUT
SK(O)
or
≤ 2.5ns; t
PHL2 -
t
SK(T)
PHL2
t
|t
SK(o)
of the Pulse Generator.
PHL2 -
t
PHL1
t
t
PHL1
PHL2
R
Switch
GND
t
t
≤ 2.5ns
SK(t)
PHL1
6V
|
V
3V
1.5V
0V
V
1.5V
V
V
1.5V
|
OL
OH
OL
OH
V
V
V
3V
1.5V
0V
1.5V
1.5V
V
OH
OL
OH
OL