5T9310NLGI Integrated Device Technology (Idt), 5T9310NLGI Datasheet

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5T9310NLGI

Manufacturer Part Number
5T9310NLGI
Description
Clock Driver 2-IN LVDS 40-Pin VFQFPN EP Tray
Manufacturer
Integrated Device Technology (Idt)
Datasheet

Specifications of 5T9310NLGI

Package
40VFQFPN EP
Configuration
1 x 2:1
Input Signal Type
CML|eHSTL|HSTL|LVDS|LVEPECL|LVPECL|LVTTL
Maximum Output Frequency
1000 MHz
Maximum Quiescent Current
295 mA
Operating Supply Voltage
2.5 V
© 2005 Integrated Device Technology, Inc.
FEATURES:
• Guaranteed Low Skew < 25ps (max)
• Very low duty cycle distortion < 125ps (max)
• High speed propagation delay < 1.75ns (max)
• Up to 1GHz operation
• Selectable inputs
• Hot insertable and over-voltage tolerant inputs
• 3.3V / 2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V),
• Selectable differential inputs to ten LVDS outputs
• Power-down mode
• 2.5V V
• Available in VFQFPN package
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
APPLICATIONS:
• Clock distribution
FUNCTIONAL BLOCK DIAGRAM
IDT5T9310
2.5V LVDS 1:10 CLOCK BUFFER TERABUFFER II
CML, or LVDS input interface
DD
SEL
PD
GL
G1
G2
A1
A1
A2
A2
2.5V LVDS 1:10
CLOCK BUFFER
TERABUFFER™ II
1
1
0
DESCRIPTION:
input to ten LVDS outputs. The fanout from a differential input to ten LVDS outputs
reduces loading on the preceding driver and provides an efficient clock
distribution network. The IDT5T9310 can act as a translator from a differential
HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to
LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be used to
translate to LVDS outputs. The redundant input capability allows for an
asynchronous change-over from a primary clock source to a secondary clock
source. Selectable reference inputs are controlled by SEL.
disabled, the outputs will drive to the value selected by the GL pin. Multiple power
and grounds reduce noise.
The IDT5T9310 2.5V differential clock buffer is a user-selectable differential
The IDT5T9310 outputs can be asynchronously enabled/disabled. When
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
INDUSTRIAL TEMPERATURE RANGE
MARCH 2005
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
Q7
Q7
Q8
Q8
Q9
Q9
Q10
Q10
IDT5T9310
DSC-6175/18

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5T9310NLGI Summary of contents

Page 1

IDT5T9310 2.5V LVDS 1:10 CLOCK BUFFER TERABUFFER II FEATURES: • Guaranteed Low Skew < 25ps (max) • Very low duty cycle distortion < 125ps (max) • High speed propagation delay < 1.75ns (max) • 1GHz operation • Selectable ...

Page 2

IDT5T9310 2.5V LVDS 1:10 CLOCK BUFFER TERABUFFER II PIN CONFIGURATION GND ...

Page 3

IDT5T9310 2.5V LVDS 1:10 CLOCK BUFFER TERABUFFER II ABSOLUTE MAXIMUM RATINGS Symbol Description V Power Supply Voltage DD V Input Voltage I V Output Voltage ( Storage Temperature STG T Junction Temperature J NOTES: 1. Stresses greater than ...

Page 4

IDT5T9310 2.5V LVDS 1:10 CLOCK BUFFER TERABUFFER II DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR LVTTL Symbol Parameter Input Characteristics I Input HIGH Current IH I Input LOW Current IL V Clamp Diode Voltage Input Voltage IN ...

Page 5

IDT5T9310 2.5V LVDS 1:10 CLOCK BUFFER TERABUFFER II DIFFERENTIAL INPUT AC TEST CONDITIONS FOR HSTL Symbol Parameter V Input Signal Swing (1) DIF V Differential Input Signal Crossing Point X D Duty Cycle H V Input Timing Measurement Reference Level ...

Page 6

IDT5T9310 2.5V LVDS 1:10 CLOCK BUFFER TERABUFFER II DIFFERENTIAL INPUT AC TEST CONDITIONS FOR LVDS Symbol Parameter V Input Signal Swing (1) DIF V Differential Input Signal Crossing Point X D Duty Cycle H V Input Timing Measurement Reference Level ...

Page 7

IDT5T9310 2.5V LVDS 1:10 CLOCK BUFFER TERABUFFER II AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Symbol Parameter Skew Parameters Same Device Output Pin-to-Pin Skew Pulse Skew ( Part-to-Part ...

Page 8

IDT5T9310 2.5V LVDS 1:10 CLOCK BUFFER TERABUFFER II DIFFERENTIAL AC TIMING WAVEFORMS 1/ [1:2] [1:2] t PLH SK( NOTES: 1. Pulse skew is calculated using the following expression ...

Page 9

IDT5T9310 2.5V LVDS 1:10 CLOCK BUFFER TERABUFFER [1:2] [1: PLH Differential Gate Disable/Enable Showing Runt Pulse Generation NOTE shown possible to generate runt pulses on gate ...

Page 10

IDT5T9310 2.5V LVDS 1:10 CLOCK BUFFER TERABUFFER II TEST CIRCUITS AND CONDITIONS Pulse Generator DIFFERENTIAL INPUT TEST CONDITIONS ~50Ω Transmission Line ~50Ω Transmission Line Test Circuit for Differential Input Symbol V = 2.5V ± 0.2V DD ...

Page 11

IDT5T9310 2.5V LVDS 1:10 CLOCK BUFFER TERABUFFER II Pulse Generator A Pulse Generator A Test Circuit for Propagation, Skew, and Gate Enable/Disable Timing NOTES: 1. Specifications only apply to "Normal Operations" test condition. The T 2. The scope inputs are ...

Page 12

IDT5T9310 2.5V LVDS 1:10 CLOCK BUFFER TERABUFFER II RECOMMENDED LANDING PATTERN NOTE: All dimensions are in millimeters. INDUSTRIAL TEMPERATURE RANGE NL 40 pin 12 ...

Page 13

IDT5T9310 2.5V LVDS 1:10 CLOCK BUFFER TERABUFFER II ORDERING INFORMATION XX XXXXX IDT Package Device Type CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 X Process I -40°C to +85°C (Industrial) Thermally Enhanced Plastic Very Fine Pitch ...

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