83940AY-02LF Integrated Device Technology (Idt), 83940AY-02LF Datasheet

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83940AY-02LF

Manufacturer Part Number
83940AY-02LF
Description
Clock Driver 2-IN LVCMOS/LVTTL 32-Pin LQFP Tray
Manufacturer
Integrated Device Technology (Idt)
Datasheet

Specifications of 83940AY-02LF

Package
32LQFP
Configuration
1 x 2:1
Input Signal Type
HCSL/LVCMOS/LVDS/LVHSTL/LVPECL/LVTTL/SSTL
Maximum Output Frequency
200 MHz
Operating Supply Voltage
2.5|3.3 V
G
The ICS83940-02 is a low skew, 1-to-18 Fanout Buffer . The
83940-02 has two selectable clock inputs. The CLK0,
nCLK0 pair can accept most standard differential input
levels. The single ended clock input accepts LVCMOS or
LVTTL input levels. The low impedance LVCMOS/LVTTL
outputs are designed to drive 50Ω series or parallel
terminated transmission lines. The effective fanout can be
increased from 18 to 36 by utilizing the ability of the
outputs to drive two series terminated lines.
The ICS83940-02 is characterized at full 3.3V, full 2.5V and
mixed 3.3V input and 2.5V output operating supply modes.
Guaranteed output and part-to-part skew characteristics
make the ICS83940 ideal for those clock distribution
applications demanding well defined performance and
repeatability.
B
83940AY-02
LVCMOS_CLK
LOCK
ENERAL
CLK_SEL
nCLK0
CLK0
D
IAGRAM
D
ESCRIPTION
0
1
D
Q0:Q17
IFFERENTIAL
www.idt.com
1
P
LVCMOS_CLK
F
• 18 LVCMOS/LVTTL outputs, 7Ω typical output impedance
• Selectable LVCMOS_Clock or CLK0, nCLK0 input pair
• LVCMOS_CLK supports the following input types:
• CLK0, nCLK0 pair can accept the following differential
• Maximum output frequency: 200MHz
• Output skew: 120ps (maximum)
• Part-to-part skew: 850ps (maximum)
• Output supply modes:
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
IN
LVCMOS or LVTTL
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
Core/Output
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
EATURES
CLK_SEL
-
A
TO
GND
GND
nCLK
V
CLK
V
DDO
SSIGNMENT
DD
-LVCMOS/LVTTL F
7mm x 7mm x 1.4mm package body
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
ICS83940-02
32-Lead LQFP
Y Pacakge
Top View
L
ICS83940-02
OW
S
ANOUT
KEW
24
23
22
21
20
19
18
17
REV. A AUGUST 4, 2010
, 1-
Q6
Q7
Q8
V
Q9
Q10
Q11
GND
DDO
B
TO
UFFER
-18

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83940AY-02LF Summary of contents

Page 1

... B D LOCK IAGRAM CLK_SEL CLK0 0 nCLK0 LVCMOS_CLK 1 83940AY- -LVCMOS/LVTTL F IFFERENTIAL TO F EATURES • 18 LVCMOS/LVTTL outputs, 7Ω typical output impedance • Selectable LVCMOS_Clock or CLK0, nCLK0 input pair • LVCMOS_CLK supports the following input types: LVCMOS or LVTTL • ...

Page 2

... ABLE IN ESCRIPTIONS ABLE IN HARACTERISTICS 3A ABLE LOCK ELECT UNCTION 3B ABLE LOCK NPUT UNCTION — 0 — 0 — 0 — 0 — — — — 83940AY- -LVCMOS/LVTTL F IFFERENTIAL ABLE ABLE — — " www.idt.com 2 ICS83940- KEW ANOUT Ω REV. A AUGUST 4, 2010 - UFFER . KΩ KΩ Ω " ...

Page 3

... D - -LVCMOS/LVTTL F IFFERENTIAL TO 4.6V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the + 0 device. These ratings are stress specifications only. Functional + 0.5V operation of product at these conditions or any conditions be- DDO yond those listed in the DC Characteristics or AC Character- 47.9° ...

Page 4

... T 4C ABLE IFFERENTIAL HARACTERISTICS 5A ABLE HARACTERISTICS 83940AY- -LVCMOS/LVTTL F IFFERENTIAL 3.3V±5% 2.5V±5 3.3V±5 0° 70° DDO ≤ www.idt.com 4 ICS83940- KEW ANOUT = 3V±5% 2.5V±5 0° DDO REV. A AUGUST 4, 2010 - UFFER 70° µ A µ A µ A µ ...

Page 5

... T 5B 3.3V±5%; V ABLE HARACTERISTICS 5C ABLE HARACTERISTICS 83940AY- -LVCMOS/LVTTL F IFFERENTIAL TO = 2.5V±5 0° DDO ≤ 2.5V±5 0° 70° DDO ≤ www.idt.com 5 ICS83940- KEW B ANOUT 70° REV. A AUGUST 4, 2010 -18 TO UFFER ...

Page 6

... UTPUT OAD 2.05V±5% 1.25V± DDO LVCMOS GND -1.25V±5% 3.3V C /2. ORE UTPUT OAD V DDx DDx sk( UTPUT KEW 83940AY- -LVCMOS/LVTTL F IFFERENTIAL EASUREMENT 1.25V±5% SCOPE DDO Qx LVCMOS GND -1.25V±5% C 2.5V C /2.5V O EST IRCUIT ORE V DD SCOPE nCLK0 Qx CLK0 ...

Page 7

... Clock t Outputs UTPUT ISE ALL IME V DDO 2 Q0:Q17 Pulse Width t PERIOD t PW odc = t PERIOD UTPUT UTY YCLE ULSE IDTH 83940AY- -LVCMOS/LVTTL F IFFERENTIAL TO LVCMOS_CLK nCLK0 80% CLK0 20 Q0:Q17 P ROPAGATION ERIOD www.idt.com 7 ICS83940- KEW B ANOUT DDO ELAY REV. A AUGUST 4, 2010 -18 TO UFFER ...

Page 8

... Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio Single Ended Clock Input F IGURE 83940AY- -LVCMOS/LVTTL F IFFERENTIAL TO A ...

Page 9

... R5,R6 locate near the driver pin. F 2E. CLK/ CLK I D IGURE N NPUT RIVEN BY 3.3V LVPECL D RIVER WITH 83940AY- -LVCMOS/LVTTL F IFFERENTIAL TO examples only. Please consult with the vendor of the driver and V must meet component to confirm the driver termination requirements. For OH example in Figure 2A, the input termination applies for LVHSTL drivers ...

Page 10

... VDDO (U1-16) (U1-21) (U1- 0.1u 0.1u 0.1u 83940AY- -LVCMOS/LVTTL F IFFERENTIAL TO input signals. In this example, this input is driven by a 3.3V =3.3V. The LVPECL driver. For the LVCMOS output, a termination example CC is shown in this schematic. For more termination approaches, please refer to the LVCMOS Termination Application Note. ...

Page 11

... JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs RANSISTOR OUNT The transistor count for ICS83940-02 is: 4270 83940AY- -LVCMOS/LVTTL F IFFERENTIAL ELIABILITY NFORMATION ...

Page 12

... ACKAGE UTLINE UFFIX FOR ABLE ACKAGE θ θ θ θ θ EFERENCE OCUMENT 83940AY- -LVCMOS/LVTTL F IFFERENTIAL TO LQFP EAD D IMENSIONS ° JEDEC P 95, MS-026 UBLICATION www.idt.com 12 ICS83940- KEW TO B ANOUT UFFER ° REV. A AUGUST 4, 2010 -18 ...

Page 13

... Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. 83940AY-02 D ...

Page 14

... 83940AY- -LVCMOS/LVTTL F IFFERENTIAL www.idt.com 14 ICS83940- KEW ANOUT REV. A AUGUST 4, 2010 - UFFER ...

Page 15

... Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA 83940AY- -LVCMOS/LVTTL F ...

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