74HC4060N NXP Semiconductors, 74HC4060N Datasheet - Page 2

• Manufacturer Part Number: 74HC4060N
• Description: Counter Single 14-Bit Binary UP 16-Pin PDIP Bulk
• Manufacturer: NXP Semiconductors
• Type: Binaryr

Specifications of 74HC4060N

• Package: 16PDIP
• Logic Function: Counter
• Logic Family: HC
• Operation Mode: UP Counter
• Direction Type: Uni-Directional
• Number Of Element Outputs: 10
• Number Of Elements Per Chip: 1
• Typical Operating Supply Voltage: 5 V
• Operating Temperature: -40 to 125 °C
• Counter Type: Binary
• Clock Frequency: 95MHz
• Count Maximum: 14
• Supply Voltage Range: 2V To 6V
• Logic Case Style: DIP
• No. Of Pins: 16
• Operating Temperature Range: -40°C To +125°C
• Svhc: No SVHC
• Base Number: 74
• Rohs Compliant: Yes
• Dc: 06+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Philips Semiconductors
FEATURES
GENERAL DESCRIPTION
The 74HC/HCT4060 are high-speed Si-gate CMOS
devices and are pin compatible with “4060” of the “4000B”
series. They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT4060 are 14-stage ripple-carry
counter/dividers and oscillators with three oscillator
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. For HC the condition is V
3. For formula on dynamic power dissipation see next pages.
ORDERING INFORMATION
See
December 1990
SYMBOL PARAMETER
t
t
f
C
C
PHL/
PHL
max
All active components on chip
RC or crystal oscillator configuration
Output capability: standard (except for R
I
14-stage binary ripple counter with oscillator
I
PD
CC
f
f
C
V
For HCT the condition is V
i
o
“74HC/HCT/HCU/HCMOS Logic Package Information”
CC
PD
= input frequency in MHz
L
t
category: MSI
= output frequency in MHz
(C
PLH
= output load capacitance in pF
P
= supply voltage in V
is used to determine the dynamic power dissipation (P
L
D
= C
V
propagation delay
maximum clock frequency
input capacitance
power dissipation capacitance per package
amb
CC
PD
RS to Q
Q
MR to Q
2
n
= 25 C; t
to Q
V
f
o
CC
) = sum of outputs
n+1
3
2
n
f
r
i
= t
I
I
f
= GND to V
= GND to V
= 6 ns
(C
L
V
CC
2
TC
CC
CC
and C
f
o
) where:
1.5 V
TC
)
2
.
terminals (RS, R
Q
master reset (MR).
The oscillator configuration allows design of either RC or
crystal oscillator circuits. The oscillator may be replaced by
an external clock signal at input RS. In this case keep the
other oscillator pins (R
The counter advances on the negative-going transition of
RS. A HIGH level on MR resets the counter (Q
Q
In the HCT version, the MR input is TTL compatible, but
the RS input has CMOS input switching levels and can be
driven by a TTL output by using a pull-up resistor to V
CONDITIONS
C
notes 1, 2 and 3
9
11
D
L
and Q
= 15 pF; V
in W):
to Q
13
11
= LOW), independent of other input conditions.
to Q
CC
13
TC
= 5 V
) and an overriding asynchronous
and C
TC
and C
TC
HC
31
6
17
87
3.5
40
), ten buffered outputs (Q
74HC/HCT4060
TYPICAL
TC
) floating.
Product specification
HCT
31
6
18
88
3.5
40
3
UNIT
ns
ns
ns
MHz
pF
pF
to Q
9
3
and
CC
to
.