74HC377PW-T NXP Semiconductors, 74HC377PW-T Datasheet - Page 2

• Manufacturer Part Number: 74HC377PW-T
• Description: Flip Flop D-Type Bus Interface Pos-Edge 1-Element 20-Pin TSSOP T/R
• Manufacturer: NXP Semiconductors

Specifications of 74HC377PW-T

• Package: 20TSSOP
• Logic Function: D-Type Bus Interface
• Logic Family: HC
• Number Of Element Outputs: 8
• Number Of Elements Per Chip: 1
• Output Signal Type: Single-Ended
• Typical Operating Supply Voltage: 5 V
• Operating Temperature: -40 to 125 °C

Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. For HC the condition is V
ORDERING INFORMATION
See
December 1990
t
f
C
C
PHL
max
Ideal for addressable register applications
Data enable for address and data synchronization
applications
Eight positive-edge triggered D-type flip-flops
See “273” for master reset version
See “373” for transparent latch version
See “374” for 3-state version
Output capability: standard
I
Octal D-type flip-flop with data enable;
positive-edge trigger
I
PD
CC
SYMBOL
f
f
C
V
For HCT the condition is V
i
o
“74HC/HCT/HCU/HCMOS Logic Package Information”
/ t
CC
PD
L
category: MSI
= output frequency in MHz
= input frequency in MHz
(C
PLH
= output load capacitance in pF
P
is used to determine the dynamic power dissipation (P
= supply voltage in V
L
D
= C
V
amb
CC
PD
2
= 25 C; t
propagation delay CP to Q
maximum clock frequency
input capacitance
power dissipation capacitance per flip-flop
V
f
o
CC
) = sum of outputs
2
f
r
i
= t
I
I
f
= GND to V
= GND to V
= 6 ns
(C
PARAMETER
L
V
CC
2
CC
CC
n
f
o
) where:
1.5 V
2
.
GENERAL DESCRIPTION
The 74HC/HCT377 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT377 have eight edge-triggered, D-type
flip-flops with individual D inputs and Q outputs. A common
clock (CP) input loads all flip-flops simultaneously when
the data enable (E) is LOW. The state of each D input, one
set-up time before the LOW-to-HIGH clock transition, is
transferred to the corresponding output (Q
The E input must be stable only one set-up time prior to the
LOW-to-HIGH transition for predictable operation.
D
in W):
C
notes 1 and 2
L
= 15 pF; V
CONDITIONS
CC
= 5 V
74HC/HCT377
Product specification
13
77
3.5
20
HC
TYPICAL
n
14
53
3.5
20
) of the flip-flop.
HCT
ns
MHz
pF
pF
UNIT