74LVC74AD-T NXP Semiconductors, 74LVC74AD-T Datasheet - Page 8

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74LVC74AD-T

Manufacturer Part Number
74LVC74AD-T
Description
Flip Flop D-Type Pos-Edge 2-Element 14-Pin SO T/R
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 74LVC74AD-T

Package
14SO
Logic Function
D-Type
Logic Family
LVC
Number Of Element Outputs
1
Number Of Elements Per Chip
2
Input Signal Type
Single-Ended
Output Signal Type
Differential
Set/reset
Set/Reset
Typical Operating Supply Voltage
1.8|2.5|3.3 V
Operating Temperature
-40 to 125 °C
NXP Semiconductors
74LVC74A_6
Product data sheet
Fig 8. The set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set and reset pulse widths,
V
V
V
and the nRD to nCP recovery time
M
M
OL
= 1.5 V at V
= 0.5
and V
OH
V
CC
are typical output voltage levels that occur with the output load.
CC
at V
2.7 V;
CC
< 2.7 V;
nCP input
nSD input
nRD input
nQ output
nQ output
GND
GND
GND
V
V
V
V
OH
OH
OL
OL
V
V
V
I
I
I
V
M
Rev. 06 — 4 June 2007
Dual D-type flip-flop with set and reset; positive-edge trigger
t
V
V
W
M
M
t
t
PLH
PHL
V
M
t
W
t
t
PHL
PLH
V
M
mna423
t
rec
74LVC74A
© NXP B.V. 2007. All rights reserved.
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