MT46V16M16CY-5B:K Micron Technology Inc, MT46V16M16CY-5B:K Datasheet - Page 88

• Manufacturer Part Number: MT46V16M16CY-5B:K
• Description: DRAM Chip DDR SDRAM 256M-Bit 16Mx16 2.6V 60-Pin FBGA Tray
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46V16M16CY-5B:K

• Density: 256 Mb
• Maximum Clock Rate: 400 MHz
• Package: 60FBGA
• Address Bus Width: 15 Bit
• Operating Supply Voltage: 2.6 V
• Maximum Random Access Time: 0.7 ns
• Operating Temperature: 0 to 70 °C
• Organization: 16Mx16
• Address Bus: 15b
• Access Time (max): 700ps
• Operating Supply Voltage (typ): 2.6V
• Package Type: FBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.5V
• Supply Current: 260mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Figure 51:
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN
Case 1: t AC (MIN) and t DQSCK (MIN)
Case 2: t AC (MAX) and t DQSCK (MAX)
Command
BA0, BA1
Address
DQ
DQ
DQS
DQS
CK#
CKE
A10
DM
CK
6
6
Bank READ – with Auto Precharge
t IS
t IS
NOP
T0
t IH
1
t IH
Notes:
Bank x
IS
t IS
Row
ACT
Row
1. NOP commands are shown for ease of illustration; other commands may be valid at these
2. BL = 4.
3. The READ command can only be applied at T3 if
4. Enable auto precharge.
5.
6. DO n = data-out from column n; subsequent elements are provided in the programmed
7. Refer to Figure 35 on page 70, Figure 36 on page 71, and Figure 37 on page 72 for detailed
T1
IH
t IH
times.
t
order.
DQS and DQ timing.
t CK
RP starts only after
t RCD, t RAP 3
t RAS
t RC
NOP
T2
1
t CH
t CL
t IS
READ
Bank x
4
Col n
t
RAS has been satisfied.
T3
t IH
2,3
t LZ (MIN)
CL = 2
86
NOP
T4
t RPRE
1
t LZ (MIN)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t RPRE
NOP
T5
t DQSCK (MIN)
DO
t DQSCK (MAX)
1
n
256Mb: x4, x8, x16 DDR SDRAM
t AC (MIN)
DO
t
n
t AC (MAX)
RAP is satisfied at T3.
T5n
t RP 5
NOP
T6
Transitioning Data
1
t HZ (MAX)
T6n
t RPST
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t RPST
NOP
T7
1
Operations
Don’t Care
Bank x
ACT
T8
Row
Row