MT46V32M16P-6T:F TR Micron Technology Inc, MT46V32M16P-6T:F TR Datasheet - Page 7
![DRAM Chip DDR SDRAM 512M-Bit 32Mx16 2.5V 66-Pin TSOP T/R](/photos/7/22/72288/mfg557-66-tsop_sml.jpg)
MT46V32M16P-6T:F TR
Manufacturer Part Number
MT46V32M16P-6T:F TR
Description
DRAM Chip DDR SDRAM 512M-Bit 32Mx16 2.5V 66-Pin TSOP T/R
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet
1.MT46V32M16P-5BF_TR.pdf
(91 pages)
Specifications of MT46V32M16P-6T:F TR
Density
512 Mb
Maximum Clock Rate
333 MHz
Package
66TSOP
Address Bus Width
15 Bit
Operating Supply Voltage
2.5 V
Maximum Random Access Time
0.7 ns
Operating Temperature
0 to 70 °C
Format - Memory
RAM
Memory Type
DDR SDRAM
Memory Size
512M (32Mx16)
Speed
6ns
Interface
Parallel
Voltage - Supply
2.3 V ~ 2.7 V
Package / Case
66-TSOP
Organization
32Mx16
Address Bus
15b
Access Time (max)
700ps
Operating Supply Voltage (typ)
2.5V
Package Type
TSOP
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Supply Current
195mA
Pin Count
66
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
557-1283-2
MT46V32M16P-6T:F TR
MT46V32M16P-6T:F TR
Functional Block Diagrams
Figure 3:
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
512Mb_DDR_x4x8x16_D2.fm - 512Mb DDR: Rev. N; Core DDR Rev. B 2/09 EN
BA0, BA1
A0–A12,
RAS#
CAS#
WE#
CKE
CK#
CS#
CK
15
128 Meg x 4 Functional Block Diagram
ADDRESS
REGISTER
MODE REGISTERS
CONTROL
LOGIC
15
The 512Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory
containing 536,870,912 bits. It is internally configured as a 4-bank DRAM.
COUNTER
REFRESH
13
12
2
13
ADDRESS
2
ROW-
MUX
COUNTER/
CONTROL
COLUMN-
ADDRESS
LATCH
BANK
LOGIC
13
DECODER
ADDRESS
BANK0
LATCH
ROW-
&
11
1
8192
SENSE AMPLIFIERS
(8,192 x 2,048 x 8)
DM MASK LOGIC
I/O GATING
DECODER
MEMORY
COLUMN
7
ARRAY
BANK0
2048
(x8)
BANK1
BANK2
16384
BANK3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
8
8
512Mb: x4, x8, x16 DDR SDRAM
8
LATCH
READ
Out
CK
CK
DRIVERS
WRITE
FIFO
4
4
&
Functional Block Diagrams
CK
In
COL0
MUX
MASK
DATA
COL0
8
2
1
1
4
4
GENERATOR
REGISTERS
©2000 Micron Technology, Inc. All rights reserved.
INPUT
DQS
4
1
1
4
4
DATA
1
1
4
1
DRVRS
DQS
CK
DLL
RCVRS
DQ0–DQ3
DQS
DM