MT48LC4M32B2B5-7:G Micron Technology Inc, MT48LC4M32B2B5-7:G Datasheet - Page 50

• Manufacturer Part Number: MT48LC4M32B2B5-7:G
• Description: DRAM Chip SDRAM 128M-Bit 4Mx32 3.3V 90-Pin VFBGA Tray
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC4M32B2B5-7:G

• Density: 128 Mb
• Maximum Clock Rate: 143 MHz
• Package: 90VFBGA
• Address Bus Width: 14 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Random Access Time: 17|8|5.5 ns
• Operating Temperature: 0 to 70 °C
• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 128M (4Mx32)
• Speed: 143MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 90-VFBGA
• Organization: 4Mx32
• Address Bus: 14b
• Access Time (max): 17/8/5.5ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 175mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

Timing Diagrams
Figure 33:
PDF: 09005aef80872800/Source: 09005aef80863355
128MbSDRAMx32_2.fm - Rev. L 1/09 EN
COMMAND
A0-A9, A11
BA0, BA1
DQM 0-3
CKE
A10
CLK
DQ
T = 100µs
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Power-up:
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CK stable
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DD
Initialize and Load Mode Register
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t CKS
t CMS
T0
Notes:
NOP
t CKH
High-Z
t CMH
SINGLE BANK
t CMS
ALL BANKS
t CK
1. The mode register may be loaded prior to the AUTO REFRESH cycles if desired.
2. Outputs are guaranteed High-Z after command is issued.
PRECHARGE
BANKS
T1
ALL
t CMH
Precharge
all banks
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t CMS
Tn + 1
REFRESH
AUTO
t CMH
t CH
AUTO REFRESH
NOP
t RFC
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NOP
50
t CL
To + 1
REFRESH
AUTO
AUTO REFRESH
Micron Technology, Inc., reserves the right to change products or specifications without notice.
NOP
t RFC
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NOP
t AS
t AS
LOAD MODE
Tp + 1
REGISTER
CODE
CODE
t AH
t AH
Program Mode Register
©2001 Micron Technology, Inc. All rights reserved.
128Mb: x32 SDRAM
t MRD
Tp + 2
Timing Diagrams
NOP
1, 2
Tp + 3
ACTIVE
BANK
ROW
ROW
DON’T CARE
UNDEFINED