MT48LC4M32B2P-6 IT:G Micron Technology Inc, MT48LC4M32B2P-6 IT:G Datasheet - Page 24

• Manufacturer Part Number: MT48LC4M32B2P-6 IT:G
• Description: DRAM Chip SDRAM 128M-Bit 4Mx32 3.3V 86-Pin TSOP-II Tray
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC4M32B2P-6 IT:G

• Package: 86TSOP-II
• Density: 128 Mb
• Address Bus Width: 14 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Clock Rate: 166 MHz
• Maximum Random Access Time: 17|7.5|5.5 ns
• Operating Temperature: -40 to 85 °C

Figure 11:
PDF: 09005aef80872800/Source: 09005aef80863355
128MbSDRAMx32_2.fm - Rev. L 1/09 EN
Random READ Accesses
Notes:
COMMAND
COMMAND
COMMAND
1. Each READ command may be to either bank. DQM is LOW.
Data from any READ burst may be truncated with a subsequent WRITE command, and
data from a fixed-length READ burst may be immediately followed by data from a
WRITE command (subject to bus turnaround limitations). The WRITE burst may be
initiated on the clock edge immediately following the last (or last desired) data element
from the READ burst, provided that I/O contention can be avoided. In a given system
design, there may be a possibility that the device driving the input data will go Low-Z
before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur
between the last read data and the WRITE command.
ADDRESS
ADDRESS
ADDRESS
CLK
CLK
CLK
DQ
DQ
DQ
BANK,
BANK,
T0
COL n
T0
COL n
T0
BANK,
COL n
READ
READ
READ
CL = 1
CL = 2
T1
T1
BANK,
BANK,
T1
READ
READ
READ
BANK,
COL a
COL a
COL a
D
OUT
n
CL = 3
T2
BANK,
T2
BANK,
T2
COL x
COL x
BANK,
READ
READ
READ
COL x
D
D
OUT
OUT
a
n
24
T3
T3
T3
BANK,
COL m
BANK,
COL m
READ
READ
BANK,
COL m
READ
D
D
D
OUT
OUT
OUT
x
a
n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T4
T4
T4
NOP
NOP
NOP
D
D
D
OUT
m
OUT
OUT
x
a
T5
T5
NOP
NOP
D
D
OUT
m
OUT
x
DON’T CARE
T6
NOP
D
OUT
m
©2001 Micron Technology, Inc. All rights reserved.
128Mb: x32 SDRAM
Register Definition