ZY7120L-T2 POWER ONE, ZY7120L-T2 Datasheet - Page 21

• Manufacturer Part Number: ZY7120L-T2
• Description: Module DC-DC 1-OUT 0.5V to 5.5V 20A 25-Pin SMT T/R
• Manufacturer: POWER ONE
• Type: Step Downr

Specifications of ZY7120L-T2

• Package: 25SMT
• Output Current: 20 A
• Output Voltage: 0.5 to 5.5 V
• Input Voltage: 3 to 13.2 V
• Number Of Outputs: 1

Note
protection thresholds and Power Good limits are
defined as percentages of the output voltage.
Therefore, the absolute levels of the thresholds
change when the output voltage setpoint is changed
either by output voltage adjustment or by margining.
In addition, a user can change type of protections
(latching
protections. These settings are programmed in the
GUI Fault Management window shown in Figure 40
or directly via the I
shown in Figure 41.
ZD-00194 Rev. 2.5, 01-Jul-10
Bit 7:5 LR[2:0], Load regulation configuration
Bit 4
Bit 3:0 CLS[3:0], Current limit setting
Bit 7:5 Unimplemented, read as ‘0’
Bit 4
Bit 3:2 OVPL[1:0]: Set Over Voltage Protection
Bit 1:0 UVPL[1:0]: Set Under Voltage Protection Level
R/W-0
LR2
Bit 7
Bit 7
---
U
Figure 39. Protection Configuration Register PC2
Figure 38. Current Limit Setpoint Register CLS
000: 0 V/A/Ohm
001: 0.39 V/A/Ohm
010: 0.78 V/A/Ohm
011: 1.18 V/A/Ohm
100: 1.57 V/A/Ohm
101: 1.96 V/A/Ohm
110: 2.35 V/A/Ohm
111: 2.75 V/A/Ohm
TCE, Temperature compensation enable
0: disabled
1: enabled
0h: corresponds to 37%
1h: corresponds to 47%
…
Bh: corresponds to 140%
Values higher than Bh are translated to Bh (140%)
PGLL: Set Power Good Low Level
1 = 95% of Vo
0 = 90% of Vo (Default)
Level
00 = 110% of Vo
01 = 120% of Vo
10 = 130% of Vo (Default)
11 = 130% of Vo
00 = 75% of Vo (Default)
01 = 80% of Vo
10 = 85% of Vo
that
R/W-0
LR1
---
U
or
the
non-latching)
R/W-0
LR0
---
U
2
overvoltage
C by writing into the PC1 register
R/W-1
R/W-0
PGLL
TCE
OVPL1
R/W-1
R/W-1
CLS3
or
and
OVPL0
R/W-0
R/W-0
CLS2
R = Readable bit
W = Writable bit
U = Unimplemented bit,
- n = Value at POR reset
R = Readable bit
W = Writable bit
U = Unimplemented bit,
- n = Value at POR reset
disable
read as ‘0’
read as ‘0’
www.power-one.com
undervoltage
UVPL1
R/W-1
R/W-0
CLS1
ZY7120 20A DC-DC Intelligent POL Data Sheet
certain
UVPL0
R/W-1
R/W-0
CLS0
Bit 0
Bit 0
3V to 13.2V Input
If the non-latching protection is selected, a POL will
attempt to restart every 130ms until the condition
that triggered the protection is removed.
restarting, the output voltages follow tracking and
sequencing settings.
If the latching type is selected, a POL will turn off and
stay off. The POL can be turned on after 130ms, if
the condition that caused the fault is removed and
the respective bit in the ST register was cleared, or
the Turn On command was recycled, or the input
voltage was recycled.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W-0
TRE
Bit 7
Figure 41. Protection Configuration Register PC1
TRE: Tracking fault enable
1 = enabled
0 = disabled
PVE: Phase voltage error enable
1 = enabled
0 = disabled
TRP: Tracking fault protection
1 = latching
0 = non latching
OTP: Overtemperature protection configuration
1 = latching
0 = non latching
OCP: Overcurrent protection configuration
1 = latching
0 = non latching
UVP: Undervoltage protection configuration
1 = latching
0 = non latching
OVP: Overvoltage protection configuration
1 = latching
0 = non latching
PVP: Phase Voltage Protection
1 = latching
0 = non latching
R/W-1
Figure 40. Fault Management Window
PVE
R/W-0
TRP

R/W-0
OTP
0.5V to 5.5V Output
R/W-0
OCP
Page 21 of 34
R/W-0
UVP
R = Readable bit
W = Writable bit
U = Unimplemented bit,
- n = Value at POR reset
read as ‘0’
R/W-1
OVP
When
R/W-1
PVP
Bit 0