ISPLSI 1016E-100LJ LATTICE SEMICONDUCTOR, ISPLSI 1016E-100LJ Datasheet
ISPLSI 1016E-100LJ
Specifications of ISPLSI 1016E-100LJ
Related parts for ISPLSI 1016E-100LJ
ISPLSI 1016E-100LJ Summary of contents
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... A functional superset of the ispLSI 1016 architecture, the ispLSI 1016E device adds a new global output enable pin. The basic unit of logic on the ispLSI 1016E device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1...B7 (see Figure 1). There are a total of 16 GLBs in the ispLSI 1016E device ...
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... IOCLK 1) are provided to route clocks to the GLBs and I/O cells. The Clock Distribution Network can also be driven from a special clock GLB (B0 on the ispLSI 1016E device). The logic of this GLB allows the user to create an internal clock from a combination of internal signals within the device ...
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... IH o Capacitance (T =25 C, f=1.0 MHz) A SYMBOL PARAMETER C Dedicated Input, I/O, Y1, Y2, Y3, Clock Capacitance 1 (Commercial/Industrial Clock Capacitance 2 Data Retention Specifications PARAMETER Data Retention Erase/Reprogram Cycles Specifications ispLSI 1016E 1 +1.0V CC +1.0V CC PARAMETER Commercial T = 0° 70°C A Industrial T = -40° 85°C A TYPICAL MINIMUM 20 10000 3 MIN ...
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... Refer to the Power Consumption CC section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum Specifications ispLSI 1016E Figure 2. Test Load GND to 3.0V -125 ≤ -100, -80 ≤ ...
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... Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock. 2. Refer to Timing Model in this data sheet for further details. 3. Standard 16-bit counter using GRP feedback. 4. Reference Switching Test Conditions Section. Specifications ispLSI 1016E Over Recommended Operating Conditions 1 DESCRIPTION ...
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... ORP Bypass Delay orpbp 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR Adjacent path can only be used by Lattice hard macros. Specifications ispLSI 1016E 1 DESCRIPTION 3 6 -125 ...
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... Clock Delay, Clock GLB to I/O Cell Global Clock Line iocp Global Reset t 59 Global Reset to GLB and I/O Registers gr 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. Specifications ispLSI 1016E 1 DESCRIPTION 7 -80 -125 -100 MIN. ...
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... Clock (max) + Reg co + Output gy0(max (#54 + #42 + #56) + (#42) + (#47 + #49) 9 (1.3 + 1.8 + 1.8) + (1.8) + (1.0 + 1.4) 1. Calculations are based upon timing specifications for the ispLSI 1016E- Specifications ispLSI 1016E GRP GLB Feedback Comb 4 PT Bypass #34 Reg 4 PT Bypass GLB Reg Bypass #30 #35 GRP ...
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... Figure 3. Typical Device Power Consumption vs fmax 130 120 110 100 I CC can be estimated for the ispLSI 1016E using the following equation (mA PTs * 0.52 nets * max freq * 0.004) Where PTs = Number of product terms used in design # of nets = Number of signals used in device Max freq = Highest clock frequency to the device (in MHz) The I CC estimate is based on typical conditions ( ...
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... SCLK/ Y1/RESET GND 1, 23 VCC 12 Pins have dual function capability. 2. Pins have dual function capability which is software selectable. Specifications ispLSI 1016E TQFP PIN NUMBERS 9, 10, 11, 12, Input/Output Pins - These are the general purpose I/O pins used by the logic 14, 15, 16, array. 22, ...
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... I/O 28 I/O 29 I/O 30 I/O 31 ispEN 1 SDI/ Pins have dual function capability. 2. Pins have dual function capability which is software selectable. ispLSI 1016E 44-Pin TQFP Pinout Diagram I/O 28 I/O 29 I/O 30 I/O 31 ispEN 1 SDI/ Pins have dual function capability. 2. Pins have dual function capability which is software selectable. ...
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... INDUSTRIAL ORDERING NUMBER 15 ispLSI 1016E-80LJI 15 ispLSI 1016E-80LT44I COMMERCIAL ORDERING NUMBER 7.5 ispLSI 1016E-125LJN 7.5 ispLSI 1016E-125LTN44 10 ispLSI 1016E-100LJN 10 ispLSI 1016E-100LTN44 15 ispLSI 1016E-80LJN ispLSI 1016E-80LTN44 15 INDUSTRIAL ORDERING NUMBER 15 ispLSI 1016E-80LJNI 15 ispLSI 1016E-80LTN44I 12 Grade Blank = Commercial I = Industrial Package ...
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... Revision History Date Version — 08 August 2006 09 Specifications ispLSI 1016E Change Summary Previous Lattice release. Updated for lead-free package options. 13 ...