ISPLSI 1048E-100LT LATTICE SEMICONDUCTOR, ISPLSI 1048E-100LT Datasheet - Page 5

• Manufacturer Part Number: ISPLSI 1048E-100LT
• Description: CPLD ispLSI® 1000E Family 8K Gates 192 Macro Cells 100MHz EECMOS Technology 5V 128-Pin TQFP
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of ISPLSI 1048E-100LT

• Package: 128TQFP
• Family Name: ispLSI® 1000E
• Device System Gates: 8000
• Number Of Macro Cells: 192
• Maximum Propagation Delay Time: 12.5 ns
• Number Of User I/os: 96
• Number Of Logic Blocks/elements: 48
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 100 MHz
• Operating Temperature: 0 to 70 °C

1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
PARAMETER
t
f
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
External Timing Parameters
pd2
max (Int.)
max (Ext.)
max (Tog.)
su1
co1
h1
su2
co2
h2
r1
rw1
ptoeen
ptoedis
goeen
goedis
wh
wl
su3
h3
pd1
COND.
TEST
C
C
A
A
A
A
B
B
A
–
–
–
–
–
–
–
–
–
–
–
–
4
10 GLB Reg. Clock to Output Delay
11 GLB Reg. Hold Time after Clock
12 Ext. Reset Pin to Output Delay
13 Ext. Reset Pulse Duration
14 Input to Output Enable
15 Input to Output Disable
16 Global OE Output Enable
17 Global OE Output Disable
18 External Synchronous Clock Pulse Duration, High
19 External Synchronous Clock Pulse Duration, Low
20
21
#
2
3
4
5
6
7
8
9
1
2
Data Propagation Delay, Worst Case Path
Clock Frequency with Internal Feedback
Clock Frequency with External Feedback
Clock Frequency, Max. Toggle
GLB Reg. Setup Time before Clock,4 PT Bypass
GLB Reg. Clock to Output Delay, ORP Bypass
GLB Reg. Hold Time after Clock, 4 PT Bypass
GLB Reg. Setup Time before Clock
Data Propagation Delay, 4PT Bypass, ORP Bypass
I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3)
I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)
Over Recommended Operating Conditions
DESCRIPTION
1
(
twh + twl
1
5
)
3
(
Specifications ispLSI 1048E
tsu2 + tco1
1
)
167.0
125.0
91.0
MIN. MAX.
5.5
0.0
6.5
0.0
5.0
3.0
3.0
3.0
0.0
–
–
–
–
–
–
–
–
–
-125
10.0
10.0
12.0
12.0
4.5
5.5
7.0
7.0
7.5
–
–
–
–
–
–
–
–
–
–
–
–
100.0
125.0
MIN. MAX.
71.0
6.5
0.0
7.5
0.0
6.5
4.0
4.0
3.5
0.0
–
–
–
–
–
–
–
–
–
-100
12.5
13.5
15.0
15.0
10.0
6.5
7.5
9.0
9.0
–
–
–
–
–
–
–
–
–
–
–
–
125.0
MIN. MAX.
90.9
71.0
6.5
0.0
7.5
0.0
6.5
4.0
4.0
4.0
0.0
–
–
–
–
–
–
–
–
–
-90
Table 2-0030A/1048E
12.5
13.5
15.0
15.0
10.0
6.5
7.5
9.0
9.0
–
–
–
–
–
–
–
–
–
–
–
–
UNITS
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns