ISPLSI 2032VE-110LTN44 LATTICE SEMICONDUCTOR, ISPLSI 2032VE-110LTN44 Datasheet - Page 10

• Manufacturer Part Number: ISPLSI 2032VE-110LTN44
• Description: CPLD ispLSI® 2000VE Family 1K Gates 32 Macro Cells 111MHz EECMOS Technology 3.3V 44-Pin TQFP
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of ISPLSI 2032VE-110LTN44

• Package: 44TQFP
• Family Name: ispLSI® 2000VE
• Device System Gates: 1000
• Maximum Propagation Delay Time: 13 ns
• Number Of User I/os: 32
• Number Of Logic Blocks/elements: 8
• Typical Operating Supply Voltage: 3.3 V
• Maximum Operating Frequency: 111 MHz
• Operating Temperature: 0 to 70 °C

Derivations of
Note: Calculations are based on timing specifications for the ispLSI 2032VE-300L.
ispLSI 2032VE Timing Model
GOE 0
Ded. In
Y0,1,2
I/O Pin
(Input)
Reset
t
t
t
su
h
co
2.0ns
5.2ns
1.9ns
I/O Delay
=
=
=
=
=
=
=
=
=
=
=
=
t
#21
#20
su,
Logic + Reg su - Clock (min)
(
(#20 + #22 + #26) + (#29) - (#20 + #22 + #35)
(0.4 + 0.6 + 1.9) + (0.5) - (0.4 + 0.6 + 0.4)
Clock (max) + Reg h - Logic
(
(#20 + #22 + #35) + (#30) - (#20 + #22 + #26)
(0.4 + 0.6 + 2.3) + (1.5) - (0.4 + 0.6 + 1.9)
Clock (max) + Reg co + Output
(
(#20 + #22 + #35) + (#31) + (#36 + #38)
(0.4 + 0.6 + 2.3) + (0.3) + (0.6 + 1.0)
I/O Cell
t
t
t
io +
io +
io +
t
h and
t
t
t
grp +
grp +
grp +
t
t
t
co from the Product Term Clock
t
20ptxor) + (
ptck(max)) + (
ptck(max)) + (
#45
#43, 44
#42
GRP
GRP
#22
t
gsu) - (
t
t
gh) - (
gco) + (
t
io +
t
io +
Reg 4 PT Bypass
t
orp +
XOR Delays
#33, 34,
Control
PTs
#25, 26, 27
Feedback
t
grp +
t
20 PT
35
grp +
#24
Comb 4 PT Bypass #23
9
t
ob)
OE
RE
CK
t
ptck(min))
t
Specifications ispLSI 2032VE
20ptxor)
GLB
GLB Reg Bypass
D
RST
Table 2-0042/2032VE
GLB Reg
Delay
#28
#29, 30,
31, 32
Q
ORP Bypass
Delay
ORP
ORP
#36
#37
#40, 41
0491/2000
#38,
39
I/O Cell
(Output)
I/O Pin