ISPLSI 5512VE-155LF388 LATTICE SEMICONDUCTOR, ISPLSI 5512VE-155LF388 Datasheet
ISPLSI 5512VE-155LF388
Specifications of ISPLSI 5512VE-155LF388
Related parts for ISPLSI 5512VE-155LF388
ISPLSI 5512VE-155LF388 Summary of contents
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... Global OE Pins and One Product Term OE per Macrocell Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. ...
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... Functional Block Diagram Figure 1. ispLSI 5512VE Functional Block Diagram (256-I/O Option) Input Bus Generic Logic Block VCCIO 1 TOE I/O 1 I/O 2 I/O 3 I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 28 I/O 29 I/O 30 I/O 31 I/O 32 I/O 33 I/O 34 I/O 35 I/O 44 I/O 45 I/O 46 I/O 47 ...
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... Specifications ispLSI 5512VE The ispLSI 5000VE Family features 3.3V, non-volatile in- system programmability for both the logic and the interconnect structures, providing the means to develop truly reconfigurable systems. Programming is achieved through the industry standard IEEE 1149.1-compliant Boundary Scan interface ...
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... Figure 2. ispLSI 5512VE Block Diagram (256 I/O Version I/O GLB8 160 3 160 160 CLK2 GLB9 I 160 3 160 160 CLK3 I/O GLB10 160 3 160 160 GLB11 I 160 3 160 160 68 Specifications ispLSI 5512VE GLB7 GLB6 GLB5 GLB4 768 Continued on Next Page I 160 160 ...
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... Figure 2. ispLSI 5512VE Block Diagram (256 I/O Version) -- Continued GLB12 I 160 3 160 160 I/O GLB13 160 3 160 160 I/O GLB14 160 3 160 160 GLB15 I 160 3 160 160 68 Specifications ispLSI 5512VE Continued on Previous Page GLB3 GLB2 768 GLB1 GLB0 I 160 160 3 PT ...
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... 159 PT 158 PT 157 PT 156 PT 155 PT 160 PT 161 PT 162 Specifications ispLSI 5512VE Global PTOE Bus PTSA 6 Macrocell 0 From PTSA To I/O Pad PTSA bypass PTOE PT Clock PT Reset PT Preset Shared PT Clock To GRP Shared PT Reset Global PTOE 0 ... 3 4 Macrocell 1 From PTSA To I/O Pad PTSA bypass ...
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... Figure 4. ispLSI 5000VE Macrocell PTOE GOE0 GOE1 TOE PT Clock PT Reset Shared PT Reset PT Preset speed/ power Note: Not all macrocells have I/O pads. Specifications ispLSI 5512VE Global PTOE 0 Global PTOE 1 Global PTOE 2 Global PTOE 3 PTSA bypass D PTSA Clk En Shared PT Clock CLK0 Clk ...
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... RESET (dedicated pin) IO0/TOE (shared pin) Specifications ispLSI 5512VE speed. The clock inversion is available on the remaining CLK1 - CLK3 signals. By sharing the pins with the I/O pins, CLK2 and CLK3 can not only be inverted but are also available for logic implementation through GRP signal routing ...
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... Figure 6. Boundary Scan Register Circuit for I/O Pins SCANIN BSCAN (from previous Registers cell Shift DR Clock DR Figure 7. Boundary Scan Register Circuit for Input-Only Pins Input Pin SCANIN (from previous Shift DR Clock DR Specifications ispLSI 5512VE HIGHZ EXTEST TOE BSCAN Normal Latches Function EXTEST PROG_MODE Normal Function Update DR Reset 0 SCANOUT ...
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... BSCAN test Capture register hold time t btuco BSCAN test Update reg, falling edge of clock to valid output t btuoz BSCAN test Update reg, falling edge of clock to output disable t btuov BSCAN test Update reg, falling edge of clock to output enable Specifications ispLSI 5512VE T T btsu bth T btcl ...
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... CCIO Capacitance (T =25°C,f=1.0 MHz) A SYMBOL PARAMETER C I/O Capacitance 1 C Clock Capacitance 2 C Global Input Capacitance 3 Erase Reprogram Specification PARAMETER ispLSI Erase/Reprogram Cycles Specifications ispLSI 5512VE 0°C to +70°C Commercial -40°C to +85°C Industrial A TYPICAL MINIMUM 10000 11 MIN. MAX. 3.00 3.60 3 ...
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... Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH 1. I/O voltage configuration must be set to VCC. Specifications ispLSI 5512VE Figure 9. Test Load GND to V CCIO min ≤ 1.5ns 10% to 90% 1.5V 1.5V See Figure 9 Device Table 2-0003/5KVE Output * C L includes Test Fixture and Probe Capacitance ...
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... Bus Hold Low Overdrive Current BHLO I Bus Hold High Overdrive Current BHLH I Bus Hold Trip Points BHT I Current Needed for V VCCIO CCIO 1. Pullup is capable of pulling to a minimum voltage of V Specifications ispLSI 5512VE 1 Over Recommended Operating Conditions CONDITION 100µA CCIO=min 2mA CCIO=min ...
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... External Switching Characteristics — — — — — — — — — — — Specifications ispLSI 5512VE Over Recommended Operating Conditions — — — — — — — — — — — — — — — — — — — — ...
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... External Switching Characteristics — — — — — — — — — — — Specifications ispLSI 5512VE Over Recommended Operating Conditions — — — — — — — — — — — — — — — — — — — — ...
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... Macrocell PT OE Delay t gptoe Global PT OE Delay Note: Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet for further details. Specifications ispLSI 5512VE Over Recommended Operating Conditions -155 MIN MAX MIN MAX MIN – 1.1 – ...
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... Timing Parameters (continued) BASE PARAMETER ADDER TYPE Routing Adders route Tioi Input Adders t clk1 gclk_in t clk2 gclk_in t clk3 gclk_in 1 Tioo Output Adders t t Slow Slew I/O buf LVTTL_out buf, en, dis LVCMOS25_out buf, en, dis LVCMOS33_out buf, en, dis Tbla Additional Block Loading Adders ...
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... Timing Model From Feedback t ROUTE t BLA INREG t GCLK_IN CLK t IOI t RST RST t OE GOE In/Out Delays Note: Italicized parameters are delay adders above and beyond default conditions (i.e. GRP load of one GLB, CLK0, high-speed AND Array and VCC I/O option). ...
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... I CC can be estimated for the ispLSI 5512VE using the following equation: High Speed Mode: ICC = PTs * 0.3030 nets * Fmax * 0.00273) Low Power Mode: ICC = PTs * 0.2676 nets * Fmax * 0.00273 PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Fmax = Highest Clock Frequency to the device The I CC estimate is based on typical conditions ( ...
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... If the optional output voltage is not required, this pin must be connected to the Vcc supply. Programmable pull-up resistors and bus-hold latches only draw current from this supply pins are not to be connected to any active signals, VCC or GND. Specifications ispLSI 5512VE Description 20 ...
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... Signal Configuration ispLSI 5512VE 256-Ball fpBGA (1.0mm Ball Pitch / 17.0mm x 17.0mm Body Size I/O I/O I/O I/O I/O A 113 116 121 125 126 I/O I/O I/O I/O I/O 119/ B 108 115 117 CLK2 124 I/O I/O I/O I 106 114 120 123 ...
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... Signal Configuration ispLSI 5512VE 272-Ball BGA (1.27mm Ball Pitch / 27.0mm x 27.0mm Body Size I/O I/O I/O I/O I/O 119 114 115 122 126 CLK2 I/O I/O I 116 121 125 I/O I/O I/O I 111 117 120 123 I/O I/O I GND VCC 109 ...
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... Signal Configuration ispLSI 5512VE 388-Ball fpBGA (1.0mm Ball Pitch / 23.0mm x 23.0mm Body Size I/O I/O I/O I/O I/O A GND 170 174 178 181 184 I/O I/O I/O I/O179/ I/O B GND 169 171 175 182 187 CLK2 I/O I/O I/O I/O I/O ...
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... Signal Configuration ispLSI 5512VE 388-Ball BGA (1.27mm Ball Pitch / 35.0mmx 35.0mm Body Size I/O I/O I/O I/O I/O I/O 179 GND NC 174 CLK2 183 187 189 193 I/O I/O I/O I/O I/O I/O GND GND B 175 177 180 184 188 191 ...
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... Grade Package F256 = 256-Ball fpBGA B272 = 272-Ball BGA F388 = 388-Ball fpBGA B388 = 388-Ball BGA COMMERCIAL ORDERING NUMBER ispLSI 5512VE-155LF256 ispLSI 5512VE-155LB272 ispLSI 5512VE-155LF388 ispLSI 5512VE-155LB388 ispLSI 5512VE-125LF256 ispLSI 5512VE-125LB272 ispLSI 5512VE-125LF388 ispLSI 5512VE-125LB388 ispLSI 5512VE-100LF256 ispLSI 5512VE-100LB272 ispLSI 5512VE-100LF388 ispLSI 5512VE-100LB388 ...